Optimizing CAN node bit timing to accommodate digital isolator propagation delays
Controller Area Network (CAN), standardized under ISO 11898, is widely used in industrial and automotive applications. CAN protocols such as DeviceNet or CANOpen rely on the built-in error checking and differential signaling. Galvanic isolation can further enhance robustness, offering immunity to high voltage transients at a cost of added propagation delay. Optimal configuration of CAN nodes can allow the maximum data rate and distance even when isolation is present.
Why propagation delay matters
Propagation delay can affect concurrent transmissions and arbitration between nodes. Arbitration relies on CAN signaling; a logic 0 is “dominant” (differential voltage between bus lines) and a logic 1 is “recessive” (all outputs high impedance), meaning a dominant bit will overwrite a recessive bit. All nodes monitor the bus while transmitting and stop if this occurs when they transmit a recessive bit, allowing another node to win arbitration (Node A in Figure 1).
The propagation delay must not be too large or the bus state could be monitored before the other nodes dominant state propagates. For nodes A and B in Figure 2 the round trip time is critical, TPropAB plus TPropBA, or twice the delay through the cable and transceivers, including isolation if present. Digital isolators reduce the propagation delay compared to optocouplers, but the total allowable propagation delay in a system is fixed, so adding isolation may decrease the maximum cable distance.
Compensating for propagation delay
To compensate for propagation delay added by isolation, specific CAN controller parameters can be adjusted. First a baud rate prescaler (BRP) value is set for the CAN controller clock, defining the “time quantum” (TQ) that the bit time is divided into. These fit into 3 or 4 segments as shown in Figure 3; one for synchronization and several for propagation delay (PROP) and phase segments 1 and 2 (PS1 and PS2). PS2 and the total TQ dictate the position of the sample point.
Step 1: Match clock, prescaler, and data rate
The first step for a given data rate is to check what combinations of clock and BRP allow an integer number of TQ. Examples for 1 Mbps are shown in Table 1 for an Analog Devices ADSP-BF548 Blackfin microprocessor with built-in CAN controller. Typical system clock (fsclk) values are used, with integer numbers of TQ in bold (valid clock/BRP combinations for 1 Mbps).
Step 2: Bit segment configuration
The next step is to define the bit segments and set the sample point as late as possible. For each valid option in Table 1, one TQ must be allowed for the SYNC segment, and the TSEG2 (PS2) segment must accommodate the CAN controller processing time (<1 TQ for BF548, as long as BRP > 4). TSEG1 (PROP + PS1) is 16 TQ maximum.
Figure 3 shows possible configurations for the ADSP-BF548 with the latest sample point possible for 1 Mbps. All the configurations except for 5 TQ total are at least 85% sample point, but the optimum is 10 TQ, requiring fsclk = 50 MHz with BRP = 5.
Step 3: Calculate bus length
The last step is to determine the maximum propagation delay under the optimum configuration and decide what cable length is possible with the chosen CAN transceiver/isolation. The maximum propagation delay possible is 900 ns for the processor’s optimum configuration shown in Figure 4.
The Analog Devices ADM3053 shown in Figure 1 integrates a CAN transceiver, digital isolator and isolated power. The loop delay of 250 ns includes the isolator (500 ns for two nodes). Assuming a cable propagation delay of 5 ns/m, this means a bus length of 40 metres (maximum for 1 Mbps per ISO 11898) is possible with the BF548.
Isolation adds robustness, but it will always add a propagation delay, both in the transmit and receive directions, and doubled to account for two nodes in arbitration. To compensate for this, CAN controllers may be configured for the maximum propagation delay possible. This may allow the desired data rate and bus length is possible even with isolated nodes.
About the author
Dr. Conal Watterson is a Sr. Applications Engineer in the Interface and iCoupler Digital Isolator Group at Analog Devices in Limerick, Ireland. He received a B. Eng. degree in Computer Engineering from the University of Limerick (UL) in 2003 and an M. Eng. degree in 2005 following research into fieldbus diagnostics at the Automation Research Centre (ARC) in UL. He received his Ph.D. from UL in 2010 following research on embedded software monitoring and reliability at the Circuits & Systems Research Centre (CSRC) and the Centre for Telecommunications Value-Chain Research (CTVR).