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Strategies to reduce a 3-phase BLDC motor control and drive system

Wed, 12/18/2013 - 3:23pm
Brian Chu, Product Line Marketing Manager, Analog and Interface Products Division, Microchip Technology

Highly integrated semiconductor products are not only a trend in consumer products, but also in motor-control applications. Concurrently, the share of Brushless DC (BLDC) motors is gradually increasing over other motor types in a number of markets, such as automotive and medical applications. With the demand growth and mature technology of BLDC motors, the strategies to develop BLDC motor-control systems have evolved from discrete circuits into three distinct categories. These primary approaches can be classified as Systems on Chip (SoCs), Application-Specific Standard Products (ASSPs), and Two-Chip Solutions.

These three main categories are steadily increasing in popularity with motor-system design engineers, because they reduce the number of required components and the design complexity. However, each strategy has its strengths and weaknesses. This article will examine each approach and how it balances the design tradeoffs between integration and flexibility.

A basic motor system contains three major blocks: Power Supply, Motor Driver, and Control Unit. Figure 1 depicts a traditional discrete motor-system design. A motor system typically includes a simple RISC processor with integrated Flash memory that controls gate drivers, which then drive external MOSFETs.  Alternatively, the processor can drive the motor directly via integrated MOSFETs and a voltage regulator, which powers the processor and driver.

The SoC motor driver integrates all of the blocks that are listed above. Its programmability enables its use in a variety of applications. Additionally, it is an ideal candidate for space-constrained applications where optimization is required. However, its lower processing performance and limited internal memory prevent it from being used in a motor system where advanced control is required. Another disadvantage of SoC motor-driver ICs is their limited development tools, such as the lack of a firmware development environment. This is in contrast to the abundance of easy-to-use tools that most leading microcontroller suppliers provide.

ASSP motor drivers are designed to serve in a specific area where everything is optimized for one narrowly defined application. It occupies minimum space and requires no software tuning. Additionally, it is the perfect candidate for space-constrained applications. Figure 2 shows the block diagram of a 10-pin DFN fan motor driver. Since this type of driver usually focuses on larger-quantity applications, ASSPs often offer an excellent price-performance ratio. However, this does not mean that a motor running from an ASSP driver needs to sacrifice performance. For instance, most modern ASSP motor drivers are capable of driving a BLDC motor using sensorless and sinusoidal algorithms, which previously required a high-performance microcontroller. The lack of programmability and methods to resize the drive strength limit ASSP products’ ability to be adapted for changing market demands.

Although high integration is a trend in today’s electronics, there is also a large set of applications with growing demand for two-chip solutions that feature rich analog drivers and intelligent-analog microcontrollers. This strategy allows a designer to select from a broad range of microcontrollers that enable sensor or sensorless commutation using the trapezoidal or sinusoidal drive techniques. With this approach, the companion driver chip selection is critical. An ideal companion chip should include, at least the following features:

· A high-efficiency, adjustable voltage regulator that reduces power dissipation and powers a wide range of microcontrollers

· Monitoring and housekeeping blocks that ensure safe motor operation and allow bi-directional communication between a host and a driver

· Selectable parameters that can optimize performance without any extra programming efforts

· Suitable power-rating drivers for a MOSFET or a BLDC motor

Figure 3 depicts an example two-chip solution that combines a feature-rich, 3-phase motor driver and a high-performance digital signal controller (DSC) to drive six N-channel MOSFETs for the field-oriented control of a permanent-magnet synchronous motor, or PMSM, which is a type of brushless motor. When a simple, six-step control architecture is sufficient, a lower-cost baseline 8-bit microcontroller can replace the DSC. This can be done without changing the drive circuit, when a BLDC motor with a similar power rating is selected.

In summary, SoC and ASSP motor drivers allow a motor system designer to employ minimal components while obtaining a moderate level of flexibility. However, these highly integrated solutions have their limits, such as fixed features, memory size and processing power. Table 1 compares these three main BLDC motor-control strategies.

Table 1. BLDC motor-control strategy comparison

 

SoC

ASSP

Two-Chip Solution

Programmability

Yes (Limited)

No

Yes

Flash Memory

Fixed (typically 32 KB or lower)

No

16 KB to 256 KB

PCB Space

Moderate

Small

Moderate

Pin Count

Moderate

Low

High

Controller Selection

None

None

Broad

Reusability Across Power Ratings

Moderate

Small

High

Firmware Development Tools

Limited

Not Required

Standard from Supplier

Modern motor-control and drive solutions reduce bill-of-material cost and system development time over discrete designs, without sacrificing the ability to create a system optimized for a selected BLDC motor. The hardware and firmware reference designs and libraries available from semiconductor suppliers greatly reduce the development time to bring an advanced motor-control and drive concept to market.

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