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High-speed data streaming with PXI Express platforms

Tue, 10/08/2013 - 11:08am
Louis Hsu, manager of Measurement and I/O Platform Verification and Application, ADLINK

Electronic systems, both analog and digital, are processing and managing increasing amounts of information at continually increasing data rates. The information age continues to amplify demands on developers of high accuracy and reliability systems and subsystems. A major challenge to researchers and systems developers lies in testing, debugging and servicing systems. Continuous data acquisition of high-speed and high-resolution signals, both analog and digital, is widely sought after for application in popular analytical techniques.

Communication interfaces employed in conventional standalone instrument are normally GPIB, RS-232, or LAN ports. While easy to use, they can be ineffective when transferring excessive amounts of high-speed data. Data length for these instruments is limited by internal memory size, especially when data is to be continuously acquired. Popularly used high-end instrumentation such as oscilloscopes, waveform generators, and logic analyzers utilize internal x86 computers to process massive amounts of data. Synchronization of such instruments—especially in combination—is difficult, and intrinsic acquisition features and processing functions are limited.

Since initial release of the specification in 1998, PXI technology has evolved to include the PCI Express (PCIe) bus, featuring low latency, high bandwidth and peer-to-peer communication, and unique trigger and timing synchronization capabilities, making PXI/PXI Express (PXIe) platforms and module data streaming a better alternative for high-bandwidth data streaming and acquisition applications in a wide variety of industries, including military, electronics, manufacturing, and research testing.

Data streaming architecture and considerations
Data streaming continuously transports data from/to instruments to/from host systems, either streaming to/from memory or to/from storage. Using a high-speed digitizer as an example, data generated by ADC is moved to onboard memory for temporary storage, after which it is transferred to system memory on the host controller via the PCI Express interface for post-processing. If the final destination is a storage disk, data is moved to disk without any processing. On the PXIe backplane, PCIe switches enable system interconnection and I/O expansion. Since different PXIe chassis may have different slot types, PCIe switch routing is commensurately different and may impact data throughput for each slot.


Onboard memory of modular instruments
As recently as 10 years ago, high speed PCI digitizers required large onboard memory to store data from high speed ADCs since the PCI bus provides only 132 MB/sec throughput (though often only 80MB/sec can be achieved). PCI Bus bandwidth is often inadequate for 8-bit 1 GS/s or 14-bit 200 MS/s digitizers. To increase recording time, 512 MB, 1 GB, 4 GB, or more of memory was required. Currently, although the high-speed PCIe bus provides faster data throughput, it is still preferable to have large-scale (100 MB+) memory onboard to provide adequate data buffering when the CPU/DMA controller is engaged. For example, a 1-CH 8-bit 500 MS/s digitizer with 512 MB memory can record up to 1 sec without transferring back to system memory, and with 2 GB, up to 4 sec.


Modular instrumentation bus interface
As is shown, PCI Express provides maximum advantages as a modular instrumentation bus interface. Unlike the PCI bus, which—being parallel—offers only 132 MB/s (32-bit 33 MHz) to all devices on the same bus, PCI Express’ point-to-point serial connection delivers 250 MB/s per link, per direction. To increase total bandwidth, multiple links can be grouped into X1, X4, X8 and X16 lanes. For high-speed data streaming applications, modular instrumentation equipped with a PCI Express interface is required. For low speed and low cost data streaming applications (< 80 MB/s)—while the PCI bus may be sufficient—care should be taken, since, as a parallel bus, it shares bandwidth with other devices.


PCIe routing in PXIe chassis
To increase peripheral slot count and configuration flexibility, the PXI Express chassis offers both 4-Link and 2-Link configuration routing schemes for the system slot. Four lanes per link are provided in 4-Link configuration, and—in 2-Link configurations—one link can be up to eight lanes and the other up to 16. For maximum throughput, the specific routing scheme of the PXI Express chassis must be considered. Familiarity with PXIe chassis topology can enable modular instrumentation deployment for optimum throughput.

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