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Specifying the right ultra-low IQ LDO

Fri, 07/13/2012 - 10:28am
Pawel Holeksa, Applications Engineer, Power Management ICs, ON Semiconductor

One of the key challenges that design engineers currently face is minimizing the power consumed by the system they are designing. Employment of various low power modes can help to reduce consumption levels. The choice of low drop-out (LDO) linear voltage regulators used in a system design can impact greatly on the overall power consumption. LDOs that exhibit ultra-low quiescent current (IQ) are clearly appealing in such circumstances. IQ denotes the ground current consumption when no load is applied and will contribute significantly to keeping the power budget in check. Often there is a need however to combine minimal IQ with strong dynamic performance, to ensure a stable, noise-free voltage rail. Dealing with these two factors, which are often mutually exclusive, has proved difficult. This article looks at the tradeoffs between IQ and dynamic performance that can be involved when deciding on an LDO, as well as discussing some techniques that can be utilized to get the best balance.

The dynamic performance of ultra-low IQ LDOs with equal or very similar IQ levels can radically differ. There are two main factors which determine dynamic performance in these devices. The first is the semiconductor process utilized. Most modern LDOs are implemented using advanced CMOS or BiCMOS technologies. The second is the technique implemented in the design of the LDO.
 

There are various types of ultra-low IQ LDOs based on different techniques and exhibiting different dynamic performance characteristics. These are:

1. Constant bias LDOs - Traditionally ultra-low IQ CMOS LDOs used constant biasing scheme, with the ground current consumption kept relatively constant across the available range of output currents. Such devices are very well suited to battery powered applications with less demanding performance requirements. Their primary disadvantage is relatively poor dynamic performance, in terms of load and line transients, power supply rejection ratio (PSRR), output noise, etc. Often it is possible to tweak this dynamic performance by using larger output capacitors. Figure. 1 shows how load transient overshoot and undershoot of one of these regulators is improved by increasing the COUT from 1 µF to 100 µF. Unfortunately while the transient amplitude decreased, the settling time simultaneously increases. It should also be noted that when using large output capacitors it may be necessary to add an external reverse protection diode into the system to protect the regulator from the excessive reverse current.

2. Proportional bias LDOs - To improve the relatively poor dynamic behavior of the constant bias (constant IGND) LDOs, in newer devices the ground current changes proportionally to the output current. This assures that the LDO current consumption at light loads is practically constant and corresponds very well with the IQ specification given on the product datasheet. Although the proportional bias technique provides improved dynamic parameters with respect to constant IGND LDOs, in highly demanding, precision applications requiring very clean power supply rail and ultra-low IQ this performance may still be insufficient.

3. Adaptive bias LDOs - In order to enhance dynamic parameters and still maintain ultra-low IQ a new breed of LDOs which implement a technique called adaptive ground current are now entering the market. These devices are able to boost the ground current at a certain level of output current without compromising light load efficiency. Thanks to this, the end application can benefit from good load/line transients, PSRR and output noise. Such devices are highly optimized for powering sensitive analog/ RF circuitry in environments requiring long battery life and small solution footprint.

Figure 2 shows the ground current versus output current comparison for these three types of ultra-low IQ LDOs. Each of these has a very similar IQ specification (1 µA to 1.5 µA). As their ground current dependence on the output current is very different, so is their dynamic performance.



In some cases the IQ stated on the product datasheet can be very different from the actual value measured. There are several reasons for the discrepancy between these two figures. First, in some cases the IQ value cited does not take into account the enable (EN) pin input current flowing through an internal pull-down resistor to ground. Measurements show that this internal pull-down resistance is in the order of 1 MΩ. If the EN pin is connected to the VIN pin, the ground current will be heavily influenced by the input voltage, leading to an additional current consumption due to pull-down resistance. By contrast, other devices on the market have an EN current which is independent on the input voltage. Secondly, the adaptive ground current used in some LDOs is set in such a way that the IGND starts to increase at very low output currents.

Another important, but often overlooked parameter of the LDO is the ground current consumption if it enters a dropout condition. In Li-Ion or Li-Poly battery powered products it is common to regulate the power supply with reasonably high efficiency using LDOs to produce a 3.3 V or 3.1 V output voltage. However, as the battery discharges and its voltage decays, the VIN of the LDO may approach VOUT to the point where the regulator enters its dropout region. In such cases, most of the ultra-low IQ LDOs currently available on the market will start to draw significantly higher ground current than what could be expected relying solely on the datasheet values stated. To illustrate the problem, Figure 3 shows the IGND vs. VIN for a typical ultra-low IQ LDO.


In the dropout region the LDO starts to draw up to 100 µA. To tackle this problem in power sensitive applications it may be advisable to add in a very low power supervisor IC with adjustable hysteresis to account for the battery voltage recovery after the load is removed. In some cases where the hysteresis is insufficient other voltage detectors with a latched output may be better suited. This will however result in the necessity to clear the latch using either a push button or the information from the battery charge controller.

It is not uncommon for the IQ specification given on an LDO datasheet to be for a perfect no load condition and not for the more realistic output load of 10 µA to 100 µA. Sometimes it may also be relevant to know the ground current behavior with respect to the input voltage or temperature. The ground current of some LDOs available on the market increases considerably if the input voltage decreases and the device enters into its dropout region.

Additional unexpected current consumption can have a negative effect on a design by considerably shortening its battery life. These issues can be particularly acute for designs where much of the time is spent in idle or sleep mode, with minimal current being drawn. Engineers should read the datasheet notes thoroughly for the IQ specification and where possible, examine the associated graphs of IQ vs. ILOAD before specifying a particular LDO.

The latest generation of LDOs allows reductions to be made to the current required without having to totally sacrifice dynamic performance. By utilizing advanced semiconductor technologies and sophisticated design techniques, there are now LDOs available for which these compromises are much less dramatic. However, the system designers need to be aware of the nuances of devices’ datasheets to fully understand their operation and to select best option for their specific application.

For more information, visit http://www.onsemi.com.

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