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New Tools Expand Logic Analyzer Utility for DDR Memory Validation

Tue, 05/24/2011 - 12:18pm
Brad Frieden, Agilent Technologies, www.agilent.com
The traditional role of logic analyzers in digital circuit and system debug and validation, including DDR memory systems, has been to find and fix problems, and the logic analyzer was often a tool of last resort. Previous generations of logic analyzers were considered difficult to use, and were most often turned to under high-pressure circumstances to identify and fix a problem. Recent new software tools and trigger macro improvements are changing that. New compliance and performance analysis tools and a DDR-specific trigger tool simplify logic analysis and help evaluate system performance. Now it is possible to reach for a logic analyzer and proactively check how well your memory system complies with the standards and even evaluate how efficient that memory is. With the new trigger tool, gone are the days of setting up a complex trigger just to see the memory at a particular physical address. Tools are also available to trigger on sequential bursts of data and to scan signals in a system to obtain analog views of the signals and consider qualitative signal integrity effects in designs. With these new developments, logic analyzer measurements can now expand well beyond debug, and are much simpler to make.

Classic Logic Analyzer Memory Debug Measurements
In its most rudimentary form, at least in the context of DDR memory measurements, the logic analyzer can function as a way to see DDR memory activity in a waveform view, with consideration for the proper functionality of the memory. You might be looking for a Pre-Charge followed by an Activate and then a Memory Read, complete with a burst of data. The logic analyzer can also display timing relationships in the waveform view when in a timing capture mode. Or you might need to see a memory decoder listing to determine if data has been properly written or read back with consideration for bank, row and column physical addresses.

For the examples in this article, the system under test is a memory system used in a gaming PC platform, utilizing DDR3 memory operating at 1937 GT/s. A MemTest program can drive known data in the memory system, and the logic analyzer can verify correct operation.

In this example, an Agilent U4154A logic analyzer is used as shown in Figure 1, with a connection to the target using a DDR3 interposer probe. The key logic analyzer specifications for the measurements include a maximum state capture speed of 2.5 Gb/s, which easily covers the 1937 MHz speed of the target. At the convenient probing location of a DIMM interposer with the system under test running at near 2 Gb/s, it is important to have a logic analyzer that can capture very small data valid windows. In this case, the data valid characteristic of 100mV by 100 ps on the U4154A easily satisfies the requirement. 

Figure 1. Logic analyzer system with interposer probe attached to target system.

Memtest 86 Test #5 provided specific data patterns that the logic analyzer could trigger on, capture, and display in waveform and/or listing views. Viewing the functional flow of signals is a basic operation simplified by a decoder tool that literally decodes the DDR3 bus transactions.

Triggering on an exact burst of data is a more complex trigger that has been simplified with software macros and enhanced with new hardware that allows the logic analyzer to trigger on up to 4 sequential back-to-back data bursts of specific data patterns. Triggering on exact data patterns allows the user to view specific activity or tests running on the system.
There is much more that can be learned.

Where Designers Want More
Designers want to be able to push beyond basic validation measurements and expand the use model of the logic analyzer to help make decisions regarding DDR memory compliance and performance. Information they want is contained in the trace from the logic analyzer; software tools help put the information into useful forms.

Real-time Protocol Violation Detection
A new DDR3 Protocol Violation Detector, called the “DDR3 Detective” from FuturePlus System, monitors DDR3 bus traffic continuously and as long as required, while analyzing all behavior in real-time for several hundred different potential violations of the DDR3 Protocol. The Detective triggers a scope and/or a logic analyzer when a violation is detected. Combined with a logic analyzer and scope, the ability to monitor the DDR3 bus and trigger on any protocol violation from the DDR3 Detective™ and then view all of the DDR3 Address, Command and Data traffic around the violation along with an analog view of select signals, provide total coverage for debugging to the root cause of violations. 

Figure 2. Real-time protocol violation testing with the DDR3 Detective.

Engineers can also use tools that process captured logic analyzer data so that the memory can be evaluated in comparison to the JEDEC memory standards, and so that memory operation can be easily viewed under a variety of operating conditions. This might include running various memory tests and traffic over a variety of different memory vendors’ DDR3 memory devices.

The DDR Performance Analysis Tool
The DDR Performance Analysis Tool expands the use model for the logic analyzer as well. Much useful information is present in the logic analyzer data, but it is not easily recognizable without additional processing and appropriate display. One basic characteristic of a memory system is that under various conditions, you would expect a certain percentage of the time to be filled with Memory Reads, Memory Writes, Activates, Pre-Charge and so on.

The DDR Performance Analysis Tool, shown in Figure 3, processes captured data and provides a graphical representation of memory usage. Here we see that the profile of memory usage was 4.8 percent Reads, 2.4 percent Writes, 1.1 percent Activates, and most of the rest of the time in Deselect. This test was run with a particular memory type. You could run this test under a number of conditions where you intend for the memory to behave a certain way in response to certain input parameters and resultant memory programming. You could also run the test with a variety of memory types.

The DDR Performance Analysis Tool offers a number of other useful insights into memory performance, including memory efficiency, and memory space coverage. 

Figure 3. Distribution measurement of memory functions.

The DDR Trigger Tool
Designers often need to trigger the logic analyzer to capture on a physical address value of the memory. There are tools that can allow conversion of a physical address back into the Bank, Row and Column addresses. A logic analyzer traditionally requires that you enter each of those address values to build a complex trigger.

What does such a trigger look like? First you must find an “Activate” on the correct Bank Address and Row Address, followed by a Read or Write with the right Column Address. Setting that up can feel complicated and time-consuming, but with the DDR Trigger Tool it becomes nearly automatic. This tool allows you to simply enter a physical address, and then the tool calculates the Bank, Write, and Column Addresses, and sets up the trigger for this physical address.

Burst Trigger
Burst Trigger makes it easy to set up the logic analyzer to trigger on bursts of data. The logic analyzer trigger sequencer is capable of operating at speeds up to 2.5 GHz. This makes it possible to enter a sequence of eight data words and trigger on that burst when it happens, using only one sequence level in the logic analyzer. It is possible to trigger on four back to back data bursts at speeds up to 2.5 GHz. The Burst Trigger mode is shown in use in Figure 4. 

Figure 4. Burst trigger setup and capture.

Enhanced Eye Scan
Eye Scan is helpful both for setting accurate sampling points for state capture and also for signal integrity eye measurements. The sampling point can be adjusted in 5 ps increments referenced to the input clock, and the voltage threshold is typically adjusted automatically by the logic analyzer. Eye Scan draws a picture of the analog characteristics of each DDR memory signal similar to that of an oscilloscope. This allows you a quick look across all the signals to spot any basic signal integrity problems. If any signals have suspect signal integrity, you can use an oscilloscope to view just those signals in more detail.

The 1937 GT/s Read data from this memory can be seen in the Eye Scan picture shown in Figure 5. Notice how the time shift can be seen between byte lanes characterized by the shift seen between Read Data bit 23 and 24. Relative to each other, bit 24 is more closed than bit 23. This qualitative insight helps narrow down which signals have the most eye closure. The next step would be to use a high bandwidth scope with an active probe on bit 24 for quantitative signal integrity characterization and troubleshooting.

It is also possible to import such captured scope traces directly into the logic analyzer waveform display to further assist troubleshooting by having such signals time correlated to the logic analyzer digital waveforms. 

Figure 5. Eye Scan view of Read Data bits 23 and 24, the byte lane skew, and eye closure of bit 24.

Summary
In this article we have explored how new and enhanced tools change the role a logic analyzer plays in debugging and validating DDR memory systems. The traditional role has been debugging near the end of a project, when things are going wrong and adrenaline is flowing. New compliance-aware probes and software tools simplify measurements and triggering so that the logic analyzer can be used proactively to better understand memory system operation, efficiency, and tradeoffs associated with options for memory types and memory control. It is now possible to trigger on back-to-back bursts at high data rates to further specify patterns of interest in a captured trace. Qualified bus level signal integrity, providing relative insight across all signals in the system can now be observed quickly and easily. Logic analyzers are evolving to provide more value earlier in the system validation cycle, and where they won’t have to be the tool of last resort anymore.

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