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Modern Techniques for Characterizing Phase Change Memory Materials and Devices

Tue, 03/15/2011 - 9:27am
Alex Pronin, Lead Applications Engineer, Keithley Instruments
Flash memory devices have been around in one form or another since the early 1980s; today, they’re widely used in applications such as memory cards, USB flash drives, MP3 players, and solid-state drives for popular consumer products like Apple’s MacAir laptops. However, some electronics industry experts are predicting that flash memory’s bit error problems and rising cost may mean that it will no longer be the dominant storage medium for these applications by 2015. Each burst of voltage across a flash cell during a write cycle causes degradation; as the size of the cells decreases, the damage due to programming grows worse because the voltage necessary to program the device does not scale with the lithography.

Fortunately for electronics designers and manufacturers, phase change memory (PCM), an emerging non-volatile computer memory technology, may someday be able to replace flash memory for many applications. PCM is substantially faster than flash memory, and it’s also highly reliable, offering up to 100 million write cycles, compared to just 5,000 writes per sector with flash. PCM can also be scaled to smaller dimensions than flash. This article explores the technology on which PCM devices are based, as well as modern test techniques suitable for characterizing them.

How does phase change memory work?
PCM cells are tiny chunks of a chalcogenide alloy (i.e., with at least one element from the VI group of the periodic table of the elements, plus one element from the V and IV group). These same types of materials are also widely used in the active layers of re-writable optical media such as CDs and DVDs. Through the application of heat in the form of an electrical pulse, PCM cells can be switched rapidly from an ordered crystalline phase (which has low resistance) to a disordered, amorphous phase (which has much higher resistance). The switch from the crystalline to the amorphous phase and back is triggered by melting and quick cooling (or a slightly slower process known as re-crystallization). GST (germanium, antimony, and tellurium), with a melting temperature from 500º to 600ºC, has emerged as one of the most promising materials for PCM devices.

These devices can store binary data because of the differing levels of resistivity of the crystalline and amorphous phases of these alloys. The high resistance amorphous state represents a binary 0; the low resistance crystalline state represents a 1. In the amorphous phase, the GST material has short-range atomic order and low free electron density, which means higher resistivity. This is sometimes referred to as the RESET phase because it is usually formed after a RESET operation, in which the temperature of the DUT is raised slightly above the melting point, and then the GST is suddenly quenched to cool it. The cooling rate is critical to the formation of the amorphous layer. The typical resistance of the amorphous layer can be higher than one mega-ohm.

In the crystalline phase, the GST material has long-range atomic order and high free electronic density, resulting in lower resistivity. This is also known as the SET phase because it is formed after a SET operation, in which the material’s temperature is raised above the re-crystallization temperature but below the melting point, then cooled slightly slower to allow crystalline grains to form throughout the layer. The resistance of the crystalline phase typically ranges from 1 kilo-ohm to 10 kilo-ohms. The crystalline phase is a lower energy state; when heat is applied to material in the amorphous phase and it approaches the crystallization temperature, it tends to switch to the crystalline phase spontaneously.

Some modern PCM designs and materials can achieve multiple distinct levels, such as 16 crystalline states, instead of just two, each with different electrical properties. This allows a single cell to represent multiple bits, increasing memory density substantially.

PCM device structure
In a typical GST PCM device (Figure 1), a resistor is attached to the underside of the GST layer. Heating/melting affects only the material in a small area around the tip of the resistor. Erase/RESET pulses set high resistance or logical 0 and form an area of an amorphous layer on the device. Erase/RESET pulses are higher, narrower, and steeper than Write/SET pulses. A SET pulse, which sets a logical 1, re-crystallizes the amorphous layer back to the crystalline state. 

Figure 1. Typical PCM device structure.

Characterizing PCM devices
The levels of the RESET and SET pulses used should be carefully selected to produce melting and re-crystallization. RESET pulses should raise the temperature just above the material’s melting point and then allow the material to cool rapidly to the amorphous phase. SET pulses should raise the temperature just above the re-crystallization temperature but below the melting point and allow a longer time to cool it; therefore, the pulse width and fall time for a SET pulse should be longer than for a RESET pulse. A pulse width of one microsecond or less is usually sufficient to produce enough energy either to melt PCM material or to re-crystallize it. Pulse voltages for some materials and technologies need to be as high as 6V to reach melting temperatures. Current values generally fall into the range of 0.3–3mA.

The state of the PCM technology involved determines the required minimum fall time for a RESET pulse. If the pulse fall time is longer than the required time, the material might not be quenched effectively into an amorphous phase. Although 30–50 nanoseconds is commonly required currently, future materials will likely require even shorter fall times.

Critical characterization parameters
To develop new PCM materials and refine future device designs, manufacturers will need to be able to characterize several parameters electrically with high accuracy. Cycling endurance is a measurement of how many times a memory cell can be successfully programmed to the 0 and 1 states. Newer multi-state memory cells that have additional distinct states allow packing more memory into a single cell, which will require modifications to cycling endurance test procedures.

Manufacturers must also measure the drift of a cell’s resistance over time, a test typically performed at various temperatures. The read disturb parameter is a gauge of how the “read” procedure impacts the stored state. Unless the measurement pulse is less than 0.5V, read disturb problems are likely to occur. Re-crystallization rates, now as short as several tens of nanoseconds, may soon drop to as little as a few nanoseconds, which will make measurements with short fall times increasingly important. Because the SET phase is a lower energy state, PCM materials tend to re-crystallize spontaneously. The rate of crystallization is temperature dependent; therefore, data retention can be defined as a maximum temperature at which data, the RESET state, will remain unchanged and stable for a specified time period (typically 10 years).

The resistance-current (RI) curve (Figure 2) is among the most common parameters used in PCM characterization. A precise sequence of pulses (Figure 3) is sent through the DUT to produce these curves. The first one, a RESET pulse, sets the resistance of the DUT to the high value. It is followed by a DC-read or MEASURE pulse (usually 0.5V or lower in order to avoid affecting the state of the DUT). Next, a SET pulse and another MEASURE pulse follow. The entire sequence is repeated multiple times, with the amplitude of the SET pulse being increased slowly to the value of the RESET pulse. In the RI curve in Figure 2, note the plotted values of the measured resistances after the SET or RESET pulse. These values are plotted against current in the SET pulse. RESET values are slightly higher than one mega-ohm; SET resistance values range from one mega-ohm to several kilo-ohms, depending on the value of the SET current.

Figure 2. Resistance-current (RI) curve in red.

Figure 3. Pulse sequence for creating an RI curve. The tall red curves are RESET pulses. The shorter red pulses are SET pulses. The short rectangular black pulses are the resistance (R) measurements.

To obtain I-V (current-voltage) curves (Figure 4), the voltage sent through a DUT previously RESET to its highly resistive state is swept from low to high. The dynamic switch from a high- to a low-resistive state in the presence of a load resistor produces a characteristic RI curve with a snapback, an area of negative resistance. Snapback is a side effect of the R-load technique that has long been used to obtain both RI and I-V curves rather than a feature of PCMs or of PCM testing. 

Figure 4. A current-voltage (I-V) sweep [1].

In the standard R-Load measurement technique (illustrated in Figure 5), a resistor is connected in series with the DUT, allowing current to be measured across the DUT by measuring the voltage across the load resistor. Active, high impedance probes and an oscilloscope are used to record the voltage across the load resistor. Current across the DUT will be equal to the applied voltage (VAPPLIED) minus the voltage across the device (VDEV), divided by the load resistance. The values of the load resistor usually range from one to three kilo-ohms. This technique involves a tradeoff: if the load resistance is too high, RC effects and the voltage division between the R-Load and the DUT limits this technique’s performance; however, if the resistor value is too small, it impacts the current resolution. 

Figure 5. Standard R-Load technique.

New PCM characterization technique
A current-limiting technique that eliminates the need for the load resistor has recently been developed. By tightly controlling the level of current sourced, this technique enables more accurate low current characterization in the RI curve. This new technique (Figure 6) allows taking both I-V and RI curves in a single pulse sweep by employing a high-speed pulse source and measure instrument. Keithley’s dual-channel Model 4225-PMU Ultra-Fast I-V Module is designed to source voltage and simultaneously measure both voltage and current responses with high accuracy, at rise and fall times as short as 20ns. That does not mean, however, that the instrument cannot be used for so-called “fast materials.” What is important is how fast voltage drops through the range, since it corresponds to the temperature range when crystallization occurs. Because it eliminates the load resistor, this technique also eliminates the snapback side effect. 

Figure 6. Current-limiting technique employed with ultra-fast I-V module.

The Model 4225-PMU and the Model 4225-RPM Remote Amplifier/Switches that extend the unit’s sensitivity (Figure 7) integrate with the Model 4200-SCS Semiconductor Characterization System, which not only provides the other measurement functions required for characterizing PCM devices but permits the automation of the entire testing process. 

Figure 7. Model 4225-PMU Ultra-Fast I-V Module and two Model 4225-RPM Remote Amplifier/Switches, available for the Keithley Model 4200-SCS characterization system.

Conclusion
As alternatives to flash memory devices are developed, researchers’ and manufacturers’ ability to characterize devices based on new technologies like PCM quickly and accurately is crucial. Tools and techniques now emerging will be critical to this effort. View Keithley’s online webinar on PCM devices for further details on these tools and techniques: http://event.on24.com/r.htm?e=193529&s=1&k=CBC6739B04B4BFB61F1AD6145043D7A2

References
[1] A. Pirovano, A. L. Lacaita, et al, “Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials,” IEEE Trans. Electron Devices, vol. 51, no. 5, May 2004.


Alex Pronin is a lead applications engineer with Keithley Instruments, Inc. in Cleveland, Ohio, which is part of the Tektronix test and measurement portfolio. He holds an M.S. in Physics from the Moscow Institute of Physics and Technology and a Ph.D. in Material Science from Dartmouth.
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