Traditional Versus Asymmetric Multicore Solutions

Mon, 01/24/2011 - 8:20am
Henri Tervonen, Sundar Vedantham, Ph.D., and Tareq Bustami, LSI Corporation,

When considering a communications processor for a next-generation application such as an eNodeB base station, cost and determinism requirements factor heavily in the decision. In today’s communications processors, there are two competing multicore architectural approaches in the marketplace. These two are traditional (also known as symmetric) and asymmetric multicore solutions. While both approaches combine general-purpose multicore processors with hardware accelerators, the approaches differ in the ratio of general-purpose and specialized processors, and the usage model of such resources. A symmetric multicore solution contains a large number of identical general-purpose processor cores, where any processor can run any type of thread, and a few specialized hardware accelerator engines which are run under the control of the general purpose processors. In an asymmetric model, a relatively small number of general-purpose processors are used in combination with a number of specialized accelerator engines that run very specific tasks that are computationally intensive and sensitive to latency. Furthermore, these engines are able to run autonomously without incurring any management overhead from the general purpose processors.

In a traditional multicore approach, performance demands in most applications will require jobs to be spread across multiple general-purpose cores and processing engines. This type of processing job distribution creates a lack of determinism since each job has to check in with the main processor before moving on to the next step. However, when it comes to providing deterministic performance under varying traffic loads, traditional multicore solutions do not scale well. Power consumption and performance are also definite concerns, as resource conflicts can become an issue.

Traditional Multicore

In an asymmetric multicore processor, general-purpose processing cores are coupled with a number of hardware accelerators that offload as many tasks as possible, including encryption, traffic management and deep packet inspection. The general-purpose processors provide software flexibility, while the hardware accelerators provide deterministic performance. A hardware task scheduler helps manage the flow of tasks between cores and accelerators. This approach significantly reduces the power requirements and improves efficiency since all the needed functional blocks are available within the same SoC. The strength of an asymmetric processor is its ability to delegate certain tasks to the function-specific hardware accelerators while freeing up the general purpose cores to process more complex or unspecific jobs. Due to this methodology that asymmetric multicore solutions have the ability to significantly reduce the general purpose processing core requirements.

Asymmetric Multicore  

A major benefit of using a design with a heavy emphasis on hardware accelerators is that determinism can be guaranteed under varying traffic patterns. Purely software-based CPU core performance varies widely depending upon processing requirements. Consistent throughput and fast response time due to hardware acceleration coupled with the reduced BOM cost of a SoC-based approach can differentiate asymmetric multicore-based eNodeB designs from other traditional designs. Hardware acceleration blocks can be precisely tailored to perform a specific set of tasks so that they do not have to balance their processing capacity between multiple tasks.

The LSI Axxia Communication Processor is an excellent example of an asymmetric model. It is designed for the increased performance and lower power demands of next-generation mobile and enterprise networks. Using an innovative Virtual Pipeline technology, the Axxia Communication Processor combines hardware scheduling with any-to-any packet flow that can route on-chip traffic as needed. The Axxia family delivers up to 20 Gb/s of data throughput, regardless of packet size, system loading, or protocol. 


Demands that will be imposed on networks in the near future due to new architectural deployments like Evolved Packet System (EVS), SAE (System Architecture Evolution) and LTE-Advanced will be increasingly higher than what current infrastructures are capable of handling. This requires SoC architectures that can scale well to handle rising bandwidth requirements while containing costs. Asymmetric multicore architecture provides a high-performance system that minimizes power consumption and delivers deterministic performance using a small number of powerful general-purpose cores, with broad offload capabilities using hardware acceleration engines that relieve the CPU. Next-generation asymmetric architectures like the LSI Axxia Communication Processor also deliver flexible on-chip routing technology that allows hardware job scheduling. The asymmetric multicore communication processor is uniquely positioned to handle the needs of next-generation communication infrastructures.


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