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Shrinking Design Cycles

Tue, 01/18/2011 - 10:21am
Shrikrishna Mehetre, Open-Silicon
Shrikrishna MehetreSemiconductor industry sales started with $1B in 1962 and have now reached over $225B. The initial ASIC products were mainly processors, but today the ASIC design industry has evolved to cater to every market segment, from things such as networking and imaging, to tiny biomedical devices. Before a product is placed in the market for consumers, ASICs typically go through five phases of engineering: product definition, logic design and verification, physical design, wafer/package fabrication and test. This is called the design cycle for the ASIC. 

Figure 1. Design cycle for ASICs

As shown in the Fig. 2, over the last 10 years the wafer fabrication technologies have shrunk from 180nm to 28nm/22nm allowing designers to code more and more functionality on a single die. Supporting technologies like computing, tools, package and assembly have also evolved to accommodate the growing demands from product developers. This engine of progress has been largely driven by consumers who want more for less. Additionally they also expect user-friendly features to get added to their gadgets more rapidly than ever before. Consequently, the lifespan of products has shrunk. As a result, the ASIC industry has had to deal with the challenge of shorter time to market at reduced cost and greater complexity. Every step in the design cycle has had to find ways to improve productivity to meet this challenge. 

Figure 2. Semiconductor Market Trends

Architects who used to be allowed quarters to review marketing documents are now given months to finish writing and simulating their architecture for performance improvements. Logic designers are expected to translate the architecture into RTL using tools that can accept high-level language such as C++. Physical designers have had to invent ways to lay out multimillion gate designs in half the time they took to lay out sub-million gate designs a few years ago. Likewise, fabrication, packaging and testing of ASICs have had to keep their TAT constant even with the growing number of steps required to complete these phases.

All the steps, or phases, in ASIC design depend on the closure of the previous step. And every step of an ASIC design goes through planning and execution. Planning of a step can be in parallel with execution of the previous step. For example, we can explore physical design challenges for the design and find solutions up front while logic design and verification is in progress. Similarly, test program development and assembly/test set-up can happen while physical design and manufacturing is in progress. A good example could be what Open-Silicon does with its ThinkPhysical™ philosophy. We understand and plan for clocking strategy, physical partitioning and DFT methodology during the architecture phase so that the physical implementation becomes much quicker.

While working with multiple product lines, having disciplined methodologies, automated generic flows (to give the designers a quick start) proves to be very helpful. These flows can be customized with minimal changes as per the design requirements.

Other than methods and processes, the key to a successful design is having a team with balanced skills. A combination of a team with expertise in niche areas and experts who can handle small or medium size partitions is advantageous in achieving early closure of the design. The experts in niche areas like floor planning, bump planning and full chip timing analysis ensure that full chip integration happens reliably, while other engineers concentrate on the physical design flow for the partitions in parallel with full chip implementation. This is what we call vertical engineering.

No one argues that shrinking the design cycle is needed to meet customer demands, but doing so increases risks to the design. Each design is unique, and must be looked at separately to determine the best way to shrink the design cycle for that product. Very often a combination of tools, technology and experience all play a role in delivering a chip done right and on schedule.
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