Data Acquisition Rules of the Road: Selecting High-Speed Differential ADC Drivers Part 2
Continued from Part 1
The input signal is v1; the first five harmonic-distortion products are v2 through v6; and the ADC electronic noise is vn.
The reciprocal of THD + Noise, the signal-to-noise-and-distortion ratio, or SINAD, is usually expressed in dB (Equation 24).
If SINAD is substituted for the signal-to-quantizing-noise ratio (Equation 22), we can define an effective number of bits (ENOB) that a converter would have if its signal-to-quantizing-noise ratio were the same as its SINAD (Equation 25).
ENOB can also be expressed in terms of SINAD as shown in Equation 26.
ENOB can be used to compare noise performance of an ADC driver with that of the ADC to determine its suitability to drive that ADC. A differential ADC noise model is shown in Figure 14.
Figure 14. Noise model of differential ADC driver.
The contributions to the total output noise density of each of the eight sources are shown in Equation 27 for the general case, and when ß1 = ß2 = ß.
The total output noise voltage density, vno, dm, is calculated by computing the root sum square of these components. Entering the equations into a spreadsheet is the best way to calculate the total output noise voltage density. The new ADI Diff Amp Calculator (Ref. 3), which will quickly calculate noise, gain, and other differential ADC driver behavior, is also available on the Analog Devices website.
ADC driver noise performance can now be compared with the ENOB of an ADC. An example that illustrates this procedure is to select and evaluate a differential driver with a gain of 2 for an AD9445 ADC on a 5-V supply, with a 2-V full-scale input; it is processing a direct-coupled broadband signal occupying a 50 MHz (–3-dB) bandwidth, limited with a single-pole filter. From the data-sheet listing of ENOB specifications for various conditions: for a Nyquist bandwidth of 50 MHz, ENOB = 12 bits.
The ADA4939 is a high-performance broadband differential ADC driver that can be direct-coupled. Is it a good candidate to drive the AD9445 with respect to noise? The data sheet recommends RF = 402 ? and RG = 200 ?, for a differential gain of approximately 2. The data sheet gives a total output voltage noise density for this case as 9.7 nVvHz.
First, calculate the system noise bandwidth, BN, which is the bandwidth of an equivalent rectangular low-pass filter that outputs the same noise power as the actual filter that determines the system bandwidth, for a given constant input noise power spectral density. For a one-pole filter, BN is equal to p/2 times the 3-dB bandwidth, as shown here (Equation 28).
Next, integrate the noise density over the square-root of the system bandwidth to obtain the output rms noise (Equation 29).
The amplitude of the noise is presumed to have a Gaussian distribution, so, using the common ±3s limits for the peak-to-peak noise (noise voltage swings between these limits about 99.7% of the time), the peak-to-peak output noise is calculated in Equation 30.
Now compare the driver’s peak-to-peak output noise with 1 LSB voltage of the AD9445 LSB, based on an ENOB of 12 bits and full-scale input range of 2 V, as calculated in Equation 31.
The peak-to-peak output noise from the driver is comparable to the ADC’s LSB, with respect to 12 bits of ENOB; the driver is therefore a good choice to consider in this application from the standpoint of noise. The final determination must be made by building and testing the driver/ADC combination.
Power-supply rejection (PSR) is another important specification. The role of power-supply pins as inputs to the amplifier is often ignored. Any noise on the power-supply lines or coupled into them can potentially corrupt the output signal.
For example, consider the ADA4937-1 with 50 mV p-p at 60 MHz of noise on the power line. Its PSR at 50 MHz is –70 dB. This means the noise on the power supply line would be reduced to approximately 16 µV at the amplifier output. In a 16-bit system with a 1-V full-scale input, 1 LSB is 15.3 µV; the noise from the power supply line would therefore swamp the LSB.
This situation can be improved by adding series SMT ferrite beads, L1/L2, and shunt bypass capacitors, C1/C2 (Figure 15).
Figure 15. Power-supply bypassing.
At 50 MHz, the ferrite bead has an impedance of 60 ? and the 10-nF (0.01-µF) capacitor has an impedance of 0.32 ?. The attenuator formed by these two elements provides 45.5 dB of attenuation (Equation 32).
The divider attenuation combines with the PSR of –70 dB to provide about 115 dB of rejection. This reduces the noise to approximately 90 nV p-p, well below 1 LSB.
The same approach used in the noise-analysis example can be applied to distortion analysis, comparing the ADA4939’s harmonic distortion with 1 LSB of the AD9445’s ENOB of 12 bits with 2-V full-scale output. One ENOB LSB was shown to be 488 µV in the noise analysis.
The distortion data in the ADA4939 specification table is given for a gain of 2, comparing 2nd and 3rd harmonics at various frequencies. Table 3 shows the harmonic distortion data for a gain of 2 and differential output swing of 2 V p-p.
Table 3. ADA4939 Second and Third Harmonic Distortion
The data show that harmonic distortion increases with frequency and that HD2 is worse than HD3 in the bandwidth of interest (50 MHz). Harmonic distortion products are higher in frequency than the frequency of interest, so their amplitude may be reduced by system band-limiting. If the system had a brick-wall filter at 50 MHz, only the frequencies higher than 25 MHz would be of concern, since all harmonics of higher frequencies would be eliminated by the filter. Nevertheless, we will evaluate the system up to 50 MHz, since any filtering that is present may not sufficiently suppress the harmonics, and distortion products can alias back into the signal bandwidth. Figure 16 shows the ADA4939’s harmonic distortion vs. frequency for various supply voltages with a 2 V p-p output.
Figure 16. Harmonic distortion vs. frequency.
HD2 at 50 MHz is approximately –88 dBc, relative to a 2-V p-p input signal. In order to compare the harmonic distortion level to 1 ENOB LSB, this level must be converted to a voltage as shown in Equation 33.
This distortion product is only 80 µV p-p, or 16% of 1 ENOB LSB. Thus, from a distortion standpoint, the ADA4939 is a good choice to consider as a driver for the AD9445 ADC.
Since ADC drivers are negative feedback amplifiers, output distortion depends upon the amount of loop gain in the amplifier circuit. The inherent open-loop distortion of a negative feedback amplifier is reduced by a factor of 1/(1 + LG), where LG is the available loop gain.
The amplifier’s input (error voltage) is multiplied by a large forward voltage gain, A(s), then passes though the feedback factor, ß, to the input, where it adjusts the output to minimize the error. Thus, the loop gain of this type of amplifier is A(s) × ß; as the loop gain (A(s), ß, or both) decreases, harmonic distortion increases. Voltage-feedback amplifiers, like integrators, are designed to have large A(s) at dc and low frequencies, then roll off as 1/f toward unity at a specified high frequency. As A(s) rolls off, loop gain decreases and distortion increases. Thus, the harmonic distortion characteristic is the inverse of A(s).
Current-feedback amplifiers use an error current as the feedback signal. The error current is multiplied by a large forward transresistance, T(s), which converts it to the output voltage, then passes through the feedback factor, 1/RF, which converts the output voltage to a feedback current that tends to minimize the input error current. The loop gain of an ideal current feedback amplifier is therefore T(s) × (1/RF) = T(s)/RF. Like A(s), T(s) has a large dc value and rolls off with increasing frequency, reducing loop gain and increasing the harmonic distortion.
Loop gain also depends directly upon the feedback factor, 1/RF. The loop gain of an ideal current-feedback amplifier does not depend upon a closed-loop voltage gain, so harmonic distortion performance does not degrade as closed-loop gain is increased. In a real current-feedback amplifier, loop gain does have some dependence on closed-loop gain, but not nearly to the extent that it does in a voltage-feedback amplifier. This makes a current-feedback amplifier, such as the ADA4927, a better choice than a voltage-feedback amplifier for applications requiring high closed-loop gain and low distortion. Figure 17 shows how well distortion performance holds up as closed-loop gain is increased.
Figure 17. Distortion vs. frequency and gain.
Bandwidth and Slew Rate
Effective usable bandwidth (EUBW), a new acronym analogous to ENOB (effective number of bits), describes bandwidth. Many ADC drivers and op amps boast wide bandwidth specs, but not all that bandwidth is usable. For example,–3-dB bandwidth is a conventional way to measure bandwidth, but it doesn’t mean that all the bandwidth is usable. The –3-dB bandwidth’s amplitude and phase errors can be seen a decade earlier than the actual “break” frequency. So what is the EUBW of an amplifier and how is it determined? An excellent way to determine the usable bandwidth is to consult the distortion plots on the data sheet.
Figure 18 indicates that in order to maintain greater than –80 dBc for 2nd and 3rd harmonics, this ADC driver shouldn’t be used for frequencies greater than 60 MHz. Since each application is different, the system requirements will be a guide to the appropriate driver with sufficient bandwidth and adequate distortion performance.
Figure 18. Distortion curves for ADA4937 current-feedback ADC driver.
Slew rate, a large signal parameter, refers to the max rate of change the amplifier output can track the input without excessive distortion. Consider the sine wave output at the slew rate.
The derivative (rate of change) of Equation 34 at the zero crossing, the maximum rate, is
Where dv/dt max is the slew rate, Vp is the peak voltage, and f equals the full-power bandwidth (FPBW). Solving for FPBW,
Therefore, when selecting an ADC driver, it is important to consider the gain, bandwidth, and slew rate (FPBW) to determine if the amplifier is adequate for the application.
Stability of a negative-voltage-feedback amplifier depends on the magnitude and sign of its loop gain, A(s) × ß. The differential ADC driver is a bit more complicated than a typical op-amp circuit, because it has two feedback factors. Loop gain is seen in the denominators of Equation 7 and Equation 8. Equation 37 describes the loop gain for the unmatched feedback factor case (ß1 ? ß2).
With unmatched feedback factors, the effective feedback factor is simply the average of the two feedback factors. When they are matched and defined as ß, the loop gain simplifies to A(s) × ß.
For a feedback amplifier to be stable, its loop gain must not be allowed to equal –1; or its equivalent, an amplitude of 1 with phase shift of –180°. For a voltage feedback amplifier, the point where the magnitude of loop gain equals 1 (that is, 0 dB) on its open-loop gain-frequency plot is where the magnitude of A(s) equals the reciprocal of the feedback factor. For basic amplifier applications, the feedback is purely resistive, introducing no phase shifts around the feedback loop. With matched feedback factors, the frequency independent reciprocal of the feedback factor, 1 + RF/RG, is often referred to as the noise gain. If the constant noise gain in dB is plotted on the same graph as the open-loop gain, A(s), the frequency where the two curves intersect is where the loop gain is 1, or 0 dB. The difference between the phase of A(s) at that frequency and –180°; is defined as the phase margin; for stable operation, it should be greater than or equal to 45°. Figure 19 illustrates the unity-loop-gain point and phase margin for the ADA4932 with RF/RG = 1 (noise gain = 2).
Figure 19. ADA4932 open-loop gain magnitude and phase vs. frequency.
Further examination of Figure 19 shows that the ADA4932 has approximately 50° of phase margin at a noise gain of 1 (100% feedback in each loop). While it is not practical to operate the ADC drivers at zero gain, this observation shows that the ADA4932 can operate stably at fractional differential gains (RF/RG = 0.25, noise gain = 1.25, for example). This is not true for all differential ADC drivers. Minimum stable gains can be seen in all ADC driver data sheets.
Phase margin for current-feedback ADC drivers can also be determined from open-loop responses. Instead of forward gain,
Figure 20. ADA4927 open-loop gain magnitude and phase vs. frequency.
The loop gain is 0 dB where the 300 ? feedback resistance horizontal line intersects the transimpedance magnitude curve. At this frequency, the phase of T(s) is approximately –135°, resulting in phase margin of 45°. Phase margin and stability increase as RF increases, and decrease as RF decreases. Current-feedback amplifiers should always use purely resistive feedback with sufficient phase margin.
With voltage-feedback amplifiers, it is best to use the smallest possible RF in order to minimize the phase shift due to the pole formed by RF and the summing-node capacitance. If large RF is required, that capacitance can compensated with small capacitors, CF, across each feedback resistor with values such that RFCF equals RG times the summing node capacitance.
PCB layout is necessarily one of the last steps in a design. Unfortunately, it is also one of the most often overlooked steps in a design, even though high-speed circuit performance is highly dependent on layout. A high-performance design can be compromised, or even rendered useless, by a sloppy or poor layout. Although all aspects of proper high-speed PCB design can’t be covered here, a few key topics will be addressed.
Parasitic elements rob high-speed circuits of performance. Parasitic capacitance is formed by component pads and traces and ground or power planes. Long traces without ground plane will form parasitic inductances, which can lead to ringing in transient responses and other unstable behavior. Parasitic capacitance is especially dangerous at the summing nodes of an amplifier, by introducing a pole in the feedback response, causing peaking and instability. One solution is to make sure that the areas beneath the ADC driver mounting and feedback component pads are cleared of ground and power planes throughout all layers of the board.
Minimizing undesired parasitic reactances starts with keeping all traces as short as possible. Outer layer 50-? PC-board traces on FR-4 contribute roughly 2.8 pF/inch and 7 nH/inch. These parasitic reactances increase by about 30% for inner-layer 50 ? traces. Also make sure there is ground plane under long traces to minimize trace inductance. Keeping traces short and small will help minimize both parasitic capacitance and inductance—and maintain the design’s integrity.
Power-supply bypassing is another key area of concern for layout; make sure the power supply bypass capacitors, as well as the VOCM bypass capacitor, are located as close to the amplifier pins as possible. Also, using multiple bypass capacitors on the power supplies will help ensure that a low impedance path is provided for broadband noise. Figure 21 shows a typical diff amp schematic with bypassing and output low-pass filters. The low-pass filter, limits the bandwidth and noise entering the ADC. Ideally, the power supply bypass-capacitor returns are close to the load returns; this helps reduce circulating currents in the ground plane and improves ADC driver performance. (Figure 22a and Figure 22b).
Figure 21. ADC driver with power supply bypassing and output low-pass filter.
Use of ground plane, and grounding in general, is a detailed and complex subject and beyond the scope of this article. However, there are a few key points to make, which are illustrated in Figure 22a and Figure 22b. First, connect the analog and digital grounds together at only one point and one point only. This will minimize the interaction of analog and digital currents flowing in the ground plane, which would ultimately lead to “noise” in the system. Also, terminate the analog power supply into the analog power plane and the digital power supply into the digital power plane. For mixed-signal ICs, terminate the analog returns in the analog ground plane and the digital ground return in the digital ground plane.
Figure 22(a). Component side. (b). Circuit side.
Figure 23. Mixed-signal grounding.
Refer to A Practical Guide to High-Speed Printed-Circuit-Board Layout4 for a detailed discussion about high-speed PCB layout.
We hope that the material presented here has helped you think about the many considerations that must be taken into account when you design with ADC drivers. Understanding differential amplifiers—and paying attention to the details of ADC driver design at the outset of a project—will minimize problems down the road, keeping you out of the ADC driver breakdown lane.
John Ardizzoni [email@example.com] is a senior applications engineer in ADI’s High-Speed Linear Group. John joined Analog Devices in 2002 and has more than 28 years experience in the electronics industry. He has authored numerous articles and papers and is a coauthor of the popular RAQ series.
Jonathan Pearson [firstname.lastname@example.org] has been an applications engineer in the High-Speed Amplifier Group since August 2002. Prior to joining ADI, he worked as an analog circuit and systems designer in the telecom industry. He holds a BSEE from Northeastern University, an MSEE from WPI, and two patents. Besides spending time with his family, he enjoys playing a variety of guitars, recording music, and collecting vacuum-tube guitar amplifiers and antique radios.