Data Acquisition Rules of the Road: Selecting High-Speed Differential ADC Drivers
As applications engineers, we are constantly bombarded with a variety of questions about driving high-speed analog-to-digital converters (ADCs) with differential inputs. Indeed, selecting the right ADC driver and configuration can be challenging. To make the design of robust ADC circuits somewhat easier, we’ve compiled a set of common “road hazards” and solutions. In this article, the circuit that actually drives the ADC—variously known as an ADC driver, differential amplifier, or diff amp—is assumed to be capable of handling high-speed signals.
A basic fully differential voltage-feedback ADC driver is shown in Figure 1. Two differences from a traditional op-amp feedback circuit can be seen. The differential ADC driver has an additional output terminal (VON) and an additional input terminal (VOCM). These provide great flexibility when interfacing signals to ADCs that have differential inputs.
Instead of a single-ended output, the differential ADC driver produces a balanced differential output—with respect to VOCM—between VOP and VON. “P” indicates positive and “N” indicates negative. The VOCM input controls the output common-mode voltage. As long as the inputs and outputs stay within their specified limits, the output common-mode voltage must equal the voltage applied to the VOCM input. Negative feedback and high open-loop gain cause the voltages at the amplifier input terminals, VA+ and VA–, to be essentially equal.
For the discussions that follow, some definitions are in order. If the input signal is balanced, VIP and VIN are nominally equal in amplitude and opposite in phase with respect to a common reference voltage. When the input is single-ended, one input is at a fixed voltage, and the other varies with respect to it. In either case, the input signal is defined as VIP – VIN.
The differential-mode input voltage, VIN, dm, and common-mode input voltage, VIN, cm, are defined in Equation 1
This common-mode definition is intuitive when applied to balanced inputs, but it is also valid for single-ended inputs.
The output also has a differential mode and a common mode, defined in Equation 3 and Equation 4.
Note the difference between the actual output common-mode voltage, VOUT, cm, and the VOCM input terminal, which establishes the output common-mode level.
The analysis of differential ADC drivers is considerably more complex than that of traditional op amps. To simplify the algebra, it is expedient to define two feedback factors, ß1 and ß2, as given in Equation 5 and Equation 6.
In most ADC driving applications ß1 = ß2, but the general closed-loop equation for VOUT, dm, in terms of VIP, VIN, VOCM, ß1, and ß2, is useful to gain insight into how beta mismatch affects performance. The equation for VOUT, dm, shown in Equation 7, includes the finite frequency-dependent open-loop voltage gain of the amplifier, A(s).
When ß1 ? ß2, the differential output voltage depends on VOCM—an undesirable outcome, since it produces an offset and excess noise in the differential output. The gain-bandwidth product of the voltage-feedback architecture is constant. Interestingly, the gain in the gain-bandwidth product is the reciprocal of the averages of the two feedback factors.
When ß1 = ß2 ß, Equation 7 reduces to = Equation 8.
This is a more familiar-looking expression; the ideal closed-loop gain becomes simply RF/RG when A(s) ® 8. The gain-bandwidth product is also more familiar-looking, with the “noise gain” equal to 1/ß, just as with a traditional op amp.
The ideal closed-loop gain for a differential ADC driver with matched feedback factors is seen in Equation 9.
Output balance, an important performance metric for differential ADC drivers, has two components: amplitude balance and phase balance. Amplitude balance is a measure of how closely the two outputs are matched in amplitude; in an ideal amplifier they are exactly matched. Output phase balance is a measure of how close the phase difference between the two outputs is to 180°. Any imbalance in output amplitude or phase produces an undesirable common-mode component in the output. The output balance error (Equation 10) is the log ratio of the output common-mode voltage produced by a differential input signal to the output differential-mode voltage produced by the same input signal, expressed in dB.
An internal common-mode feedback loop forces VOUT, cm to equal the voltage applied to the VOCM input, producing excellent output balance.
Terminating the Input to an ADC Driver
The input resistance of the ADC driver, whether differential or single-ended, must be greater than or equal to the desired termination resistance, so that a termination resistor, RT, can be added in parallel with the amplifier input to achieve the required resistance. All ADC drivers in the examples considered here are designed to have balanced feedback ratios, as shown in Figure 2.
Because the voltage between the two amplifier inputs is driven to a null by negative feedback, they are virtually connected, and the differential input resistance, RIN, is simply 2 × RG. To match the transmission-line resistance, RL, place resistor, RT, as calculated in Equation 11, across the differential input. Figure 3 shows typical resistances RF = RG = 200 ?, desired RL, dm = 100 ?, and RT = 133 ?.
Terminating a single-ended input requires significantly more effort. Figure 4 illustrates how an ADC driver operates with a single-ended input and a differential output.
Although the input is single-ended, VIN, dm is equal to VIN. Because resistors RF and RG are equal and balanced, the gain is unity, and the differential output, VOP – VON, is equal to the input, that is, 4 V p-p. VOUT, cm is equal to VOCM = 2.5 V and, from the lower feedback circuit, input voltages VA+ and VA– are equal to VOP/2.
Using Equation 3 and Equation 4, VOP = VOCM + VIN/2, an in-phase swing of ±1 V about 2.5 V. VON = VOCM – VIN/2, an antiphase-swing of ±1 V about 2.5 V. Thus, VA+ and VA– swing ±0.5 V about 1.25 V. The ac component of the current that must be supplied by VIN is (2 V – 0.5 V)/500 ? = 3 mA, so the resistance to ground that must be matched, looking in from VIN, is 667 ?.
The general formula for determining this single-ended input resistance when the feedback factors of each loop are matched is shown in Equation 12, where RIN, se is the single-ended input resistance.
This is a starting point for calculating the termination resistance. However, it is important to note that amplifier gain equations are based on the assumption of a zero-impedance input source. A significant source impedance that must be matched in the presence of an imbalance caused by a single-ended input inherently adds resistance only to the upper RG. To retain the balance, this must be matched by adding resistance to the lower RG, but this affects the gain.
While it may be possible to determine a closed-form solution to the problem of terminating a single-ended signal, an iterative method is generally used. The need for it will become apparent in the following example.
In Figure 5, a single-ended-to-differential gain of one, a 50 ? input termination, and feedback and gain resistors with values in the neighborhood of 200 ? are required to keep noise low.
Equation 12 provides the single-ended input resistance, 267 ?. Equation 13 indicates that the parallel resistance, RT, should be 61.5 ? to bring the 267-? input resistance down to 50 ?.
Figure 6 shows the circuit with source and termination resistances. The open-circuit voltage of the source, with its 50-? source resistance, is 2 V p-p. When the source is terminated in 50 ?, the input voltage is reduced to 1 V p-p, which is also the differential output voltage of the unity-gain driver.
This circuit may initially appear to be complete, but an unmatched resistance of 61.5 ? in parallel with 50 ? has been added to the upper RG alone. This changes the gain and single-ended input resistance, and mismatches the feedback factors. For small gains, the change in input resistance is small and will be neglected for the moment, but the feedback factors must still be matched. The simplest way to accomplish this is to add resistance to the lower RG. Figure 7 shows a Thévenin equivalent circuit in which the above parallel combination acts as the source resistance.
With this substitution, a 27.6-? resistor, RTS, is added to the lower loop to match loop feedback factors, as seen in Figure 8.
Note that the Thévenin voltage of 1.1 V p-p is larger than the properly terminated voltage of 1 V p-p, while the gain resistors are each increased by 27.6 ?, decreasing the closed-loop gain. These opposing effects tend to cancel for large resistors (>1 k?) and small gains (1 or 2), but do not entirely cancel for small resistors or higher gains.
The circuit in Figure 8 is now easily analyzed, and the differential output voltage is calculated in Equation 14.
The differential output voltage is not quite at the desired level of 1 V p-p, but a final independent gain adjustment is available by modifying the feedback resistance as shown in Equation 15.
Figure 9 shows the completed circuit, implemented with standard 1% resistor values.
Observations: Referring to Figure 9, the single-ended input resistance of the driver, RIN, se, has changed due to changes in RF and RG. The driver’s gain resistances are 200 ? in the upper loop and 200 ? + 28 ? = 228 ? in the lower loop. Calculation of RIN, se with differing gain resistance values first requires two values of beta to be calculated, as shown in Equation 16 and Equation 17.
The input resistance, RIN, se, is calculated as shown in Equation 18.
This differs little from the original calculated value of 267 ?, and does not have a significant effect on the calculation of RT, since RIN, se is in parallel with RT.
If a more-exact overall gain were necessary, higher precision or series trim resistors could be used.
A single iteration of the method described here works well for closed-loop gains of one or two. For higher gains, the value of RTS gets closer to the value of RG, and the difference between the value of RIN, se calculated in Equation 18 and that calculated in Equation 12 becomes greater. Several iterations are required for these cases.
This should not be arduous: Recently released differential amplifier calculator tools, ADIsimDiffAmp™ (Ref. 2) and ADI Diff Amp Calculator™(Ref. 3) downloadable, do all the heavy lifting; they will perform the above calculations in a matter of seconds.
Input Common-Mode Voltage Range
It may be useful to recall that VA is always a scaled-down version of the input signal (as seen in Figure 4). The input common-mode voltage range differs among amplifier types. Analog Devices high-speed differential ADC drivers have two input stage configurations, centered and shifted. The centered ADC drivers have about 1 V of headroom from each supply rail (hence centered). The shifted input stages add two transistors to allow the inputs to swing closer to the –VS rail. Figure 10 shows a simplified input schematic of a typical differential amplifier (Q2 and Q3).
The shifted input architecture allows the differential amplifier to process a bipolar input signal, even when the amplifier is powered from a single supply, making them well suited for single-supply applications with inputs at or below ground. The additional PNP transistor (Q1 and Q4) at the input shifts the input to the differential pair up by one transistor Vbe. For example, with –0.3 V applied at –IN, point A would be 0.7 V, allowing the differential pair to operate properly. Without the PNPs (centered input stage), –0.3 V at point A would reverse bias the NPN differential pair and halt normal operation.
Table 1 provides a quick reference to many specifications of Analog Devices ADC drivers. A glance reveals the drivers that feature a shifted ICMVR and those that do not.
Table 1. High-Speed ADC Driver Specifications
Input and Output Coupling: AC or DC
An ac-coupled input stage is illustrated in Figure 11.
For differential-to-differential applications with ac-coupled inputs, the dc common-mode voltage appearing at the amplifier input terminals is equal to the dc output common-mode voltage, since dc feedback current is blocked by the input capacitors. Also the feedback factors at dc are matched and exactly equal to unity. VOCM—and consequently the dc input common-mode—is very often set near midsupply. An ADC driver with centered input common-mode range works well in these types of applications, with the input common-mode voltage near the center of its specified range.
AC-coupled single-ended-to-differential applications are similar to their differential-input counterparts but have common-mode ripple—a scaled-down replica of the input signal—at the amplifier input terminals. An ADC driver with centered input common-mode range places the average input common-mode voltage near the middle of its specified range, providing plenty of margin for the ripple in most applications.
When input coupling is optional, it is worth noting that ADC drivers with ac-coupled inputs dissipate less power than similar drivers with dc-coupled inputs, since no dc common-mode current flows in either feedback loop.
AC coupling the ADC driver outputs is useful when the ADC requires an input common-mode voltage that differs substantially from that available at the output of the driver. The drivers have maximum output swing when VOCM is set near midsupply; this presents a problem when driving low-voltage ADCs with very low input common-mode voltage requirements. A simple solution to this predicament (Figure 12) is to ac-couple the connection between the driver output and the ADC input, removing the ADC’s dc common-mode voltage from the driver output, and allowing a common-mode level suitable for the ADC to be applied on its side of the ac-coupling. For example, the driver could be running on a single 5-V supply with VOCM = 2.5 V, and the ADC could be running on a single 1.8-V supply with a required input common-mode voltage of 0.9 V applied at the point labeled ADC CMV.
Drivers with shifted input common-mode ranges generally work best in dc-coupled systems operating on single supplies. This is because the output common-mode voltage gets divided down through the feedback loops, and its variable components can get close to ground, which is the negative rail. With single-ended inputs, the input common-mode voltage gets even closer to the negative rail due to the input-related ripple.
Systems running on dual supplies, with single-ended or differential inputs and ac- or dc-coupling, are usually fine with either type of input stage because of the increased headroom.
Table 2 summarizes the most common ADC driver input-stage types used with various input-coupling and power-supply combinations. However, these choices may not always be the best; each system should be analyzed on a case-by-case basis.
Table 2. Coupling and Input-Stage Options
For applications where every last millivolt of output voltage is required, Table 1 shows that quite a few ADC drivers have rail-to-rail outputs, with typical headroom ranging from a few millivolts to a few hundred millivolts, depending on the load.
Figure 13. Harmonic distortion vs. VOCM at various frequencies for the ADA4932 with a 5-V supply.
Figure 13 shows a plot of harmonic distortion vs. VOCM at various frequencies for the ADA4932, which is specified with a typical output swing to within 1.2 V of each rail (headroom). The output swing is the sum of VOCM and VPEAK of the signal (1 V). Note that the distortion starts to take off above 2.8 V (3.8-VPEAK, or 1.2 V below the 5-V rail). At the low end, distortion is still low at 2.2 V (–1 VPEAK). The same type of behavior will appear in the discussions of bandwidth and slew rate.
All ADCs inherently have quantization noise, which depends on the number of bits, n, decreasing with increasing n. Because even “ideal” converters produce quantization noise, it will be used as a benchmark against which to compare random noise and harmonic distortion. The output noise from the ADC driver should be comparable to or lower than the ADC’s random noise and distortion. Beginning with a review of the characterization of ADC noise and distortion, we will then show how to weigh ADC driver noise against the ADC’s performance.
Quantization noise occurs because the ADC quantizes analog signals having infinite resolution into a finite number of discrete levels. An n-bit ADC has 2n binary levels. The difference between one level and the next represents the finest difference that can be resolved; it is referred to as a least significant bit (LSB), or q, for quantum level. One quantum level is therefore 1/2n of the converter’s range. If a varying voltage is converted by a perfect n-bit ADC, then converted back to analog and subtracted from the ADC’s input, the difference will look like noise. It will have an rms value of (Equation 21):
From this, the logarithmic (dB) formula for the signal-to-quantizing-noise ratio of an n-bit ADC over its Nyquist bandwidth can be derived (Equation 22); it is the best achievable SNR for an n-bit converter.
Random noise in ADCs, a combination of thermal, shot, and flicker noise, is generally larger than the quantization noise. Harmonic distortion, resulting from nonlinearities in the ADC, produces unwanted signals in the output that are harmonically related to the input signals. Total harmonic distortion and noise (THD + N) is an important ADC performance metric that compares the electronic noise and harmonic distortion to an analog input that is close to the full-scale input range of the ADC. Electronic noise is integrated over a bandwidth that includes the frequency of the last harmonic to be considered. Here, the “total” in THD includes the first five harmonic-distortion components, which are root-sum-squared along with the noise (Equation 23).
Check back for Part 2