Semiconductor Highlight: Leadless Packages Empower Your Design
Leadless Packages Empower Your Design
by Ian Moulding, Business Manager, Diodes Incorporated
Semiconductor packaging has evolved from the through-hole packages of the 1970’s, through surface mount leaded packaging in the 1990’s to leadless package technologies of today such as quad/dual flat no leads (QFN/DFN), ball grid arrays (BGA) and chip scale packaging (CSP). It can be argued that it is semiconductor package innovations such as these that have allowed the industry to exploit the successive IC process shrinks and achieve product performances that were previously unobtainable.
The benefits of leadless packaging can be appreciated without the need to consider the complex multi-row BGAs. A simple three-pin discrete device such as a MOSFET is an ideal vehicle to highlight the benefits that leadless packaging can bring to an application. MOSFETs are used as switching devices that are used to conduct currents from 0.1A to 100’s of amperes at voltages up to 1000V in applications as diverse as battery management and motor control.
This article will highlight that leadless packaging is cost-effective to manufacture, utilizes board space more efficiently and is thermally more efficient than the package technology it supersedes[c1].
Leadless packaging is more efficient and environmentally friendly
From a discrete device perspective there are a number of competing leadless solutions that can be used to package MOSFETs. These include ball grid arrays, chip scale packaging and dual flat no lead packaging. However, market price pressure has made costly package material sets such as BGAs, undesirable due to expensive substrate costs. Another cost that needs to be considered, is the capital expenditure required to bring new packages into full production: tooling up new BGA and CSP substrates can substantially increase the unit cost. Consequently, the use of discrete BGAs and CSPs has been limited to applications that are performance driven and average selling price is a secondary consideration. Thus, DFN and QFN packaging has emerged as the leadless package solution that is the most cost-efficient alternative to traditional surface mount packages.
The manufacturing process flow of a typical DFN package is illustrated in Figure 1. In brief this process comprises six key process steps. Initially a leadframe is etched from copper alloy or other material and a silicon die is attached to the leadframe using a highly conductive epoxy resin. Wirebonds of aluminium (Al) or gold (Au) are then attached to make the electrical connection between the silicon die and the package pads. A halogen free compound is then moulded around the silicon and leadframe to hermetically seal the package. The moulded lead frame is then sawn to create the finished packaged product; this is then electrically tested to ensure correct functionality.
The manufacturing process flow for surface mount packages is very similar to the process flow outlined in the preceding paragraph, except that after the moulding stage there is a need to trim and form the leads. Furthermore, the structure of the leaded package requires the mould compound to fully encapsulate the leads to prevent the lead breaking away from the package during the trim and form process. This means that the leaded package has an intrinsically higher profile than the DFN/QFN packages. Furthermore, since less material is used in their manufacture these packages are greener.
DFN package technology is flexible in that the package size and the leadframe design can be tailored to meet a specific product requirement. A new package can therefore be brought to market with only the cost of the leadframe design and tooling (a few $k). This flexibility and low set up cost enables new packages to be rapidly brought to market. Conversely, significant capital expenditure and far greater time is required if a new surface mount package is to be brought to market.
Leadless packages utilize board space more efficiently
The silicon-to-footprint ratio of a MOSFET is a particularly useful figure of merit when assessing power MOSFETs and various packaging options. The silicon-to-footprint ratio is expressed as:
=The maximum electrical die area
The maximum package footprint
The SOT23 package is one of the semiconductor industry’s most widely used packages and is especially popular choice for MOSFETs. This package has a silicon-to-footprint ratio of 23[c2]% and has a printed circuit board footprint of 8mm2. The DFN2020 package from Diodes Incorporated has, by comparison, a silicon-to-footprint ratio of 42%: nearly double that of the SOT23 yet it occupies only 50% of the printed circuit board area. The DFN2020 can therefore deliver twice the performance while occupying half the space. This point clearly illustrates that leadless packages such as the DFN package, utilize printed circuit board real estate more efficiently then their surface mount counterparts. Leadless packages such as DFN, can therefore be used to increase the electrical performance of an end application without increasing printed circuit board area or, they can be used to maintain electrical performance whilst reducing the size of the printed circuit board. Adopting the latter approach can have additional cost benefits to manufacturers of original equipment (OEMs), for example migrating a printed circuit board design from surface mount devices to leadless packages could result in a printed circuit board that is 40% smaller. This could result in cost savings due to the use of smaller enclosures as well the cost efficiencies due to the use of reduced printed circuit board materials.
DFN packaging is therefore a green package solution that enables the manufacture of smaller, more compact products that utilize fewer materials.
Leadless packages improve thermal performance
A MOSFET is a switching element which when used in a circuit dissipates power due to the losses generated through its operation. These losses are primarily comprised of switching losses, the period of time the MOSFET switches on or off, and conduction losses due to the MOSFET’s on-state resistance that are incurred while the devices is conducting. This ‘wasted energy’ needs to be conducted away from the silicon die as quickly and as efficiently as possible. The thermal capabilities of the package that encapsulates the silicon die are therefore critical in achieving MOSFET performance.
The DFN package is manufactured using a highly conductive copper alloy[c3] pad as ‘the die attach pad’ which is exposed and soldered directly to the outside of the package. A highly conductive adhesive is used as an interconnect between the electrical die and the drain pad to ensure a thermally efficient and reliable contact. This, together with the larger area of contact between the DFN package and the printed circuit board, results in very low thermal impedance between junction and lead (RthJL) and junction and ambient (RthJA). The primary thermal pathway will be from the exposed drain pad into the printed circuit board. The silicon die is mounted in a similar fashion in the SOIC package but as is illustrated in Figure 2 there is no direct contact between the die and the printed circuit board. This results in three thermal pathways: through each of the leads to the printed circuit board and through the base of the package to the printed circuit board. This inefficient dissipation results in the SOIC package having a thermal impedance that is significantly higher than the leadless package. It is worth noting that leaded packages such as SOIC are not only thermally worse but difficult to design for thermal performance as the paths are not as predictable or easy to model as DFN and often one pin dominates the thermal path.
The DFN package, with its lower thermal resistance, will conduct heat away more efficiently than its surface mount counterpart. And since the maximum current that a MOSFET can handle is determined by its temperature rise the DFN package will, when compared with SOIC package, be able to dissipate more power at the same temperature - or dissipate the same power at a lower junction temperature. The primary benefit of operating a MOSFET at lower temperatures is that the MOSFET has a lower RDS(ON), which in turn means the MOSFET operates more efficiently, increasing the efficiency of the end application. Furthermore, reducing the operating temperature of a MOSFET has the added benefit of increasing the reliability of the end application; a reduction in junction temperature of just 10ºC can, in fact, double the lifetime reliability.
An analysis of Diodes Incorporated MOSFETs - the Zetex ZXMN2F34FH and the ZXMN2F34MA - can be used to illustrate the real world benefits of DFN packaging. Table 1 summarizes the key electrical and thermal properties of these two devices. A close inspection of these parameters reveals that both devices utilize the same silicon die but the lower thermal resistance (RthJL)of the DFN package enables the ZXMN2F34MA to dissipate 40% percent more power and operate at a maximum current that is 20% higher.
A note of caution though; although the package and thermal connection is better there is still a need to get the heat away from the device. So for power handling devices such as MOSFETs, good thermal management is essential to maximize the benefits of the device. If, during circuit operation, more heat is generated than can be conducted efficiently away from the silicon die then the die will overheat and is likely to go into thermal runaway. Using a DFN package instead of a leaded package, will reduce the package thermal resistance and increase the efficiency of heat dissipation, reducing the risk of thermal runaway.
In conclusion, it has been demonstrated that DFN packaging provides is the most cost-efficient leadless package option for MOSFETs. It is a fast and flexible technology that enables products to be rapidly brought to market. Furthermore, it is a green package that utilizes less material and enables end applications to be reduced in size whilst maintaining performance, significantly reducing material usage in the end application. Alternatively, the DFN package can be used to increase performance from the existing footprint. Finally, it is a thermally superior package solution enabling more efficient and cooler end applications.
As the twenty first century progresses, the DFN package is expected to proliferate into more end applications as increasing numbers of customers embrace its benefits.
About Diodes Incorporated
Diodes Incorporated (Nasdaq: DIOD), an S&P SmallCap 600 and Russell 3000 Index company, is a leading global manufacturer and supplier of high-quality application specific standard products within the broad discrete and analog semiconductor markets, serving the consumer electronics, computing, communications, industrial and automotive markets. Diodes’ products include diodes, rectifiers, transistors, MOSFETs, protection devices, functional specific arrays, amplifiers and comparators, Hall-effect sensors and temperature sensors, power management devices including LED drivers, DC-DC switching, regulators, linear voltage regulators and voltage reference along with special function devices including USB power switch, load switch, voltage supervisor and motor controllers. The Company has its corporate offices in Dallas, Texas, with a sales, marketing, engineering and logistics office in Southern California; design centers in Dallas, San Jose, Taipei, England and Germany; wafer fabrication facilities in Kansas City, Missouri and Manchester, England; two manufacturing facilities in Shanghai, China, one in Neuhaus, Germany and a joint venture facility in Chengdu, China; engineering, sales, warehouse and logistics offices in Taipei, Hong Kong and Manchester, England, and sales and support offices throughout the world. For further information, including SEC filings, visit the Company’s website at http://www.diodes.com.