Tips Help Reduce Power Demands

Wed, 01/02/2008 - 10:09am
Jon Titus, Senior Technical Editor

"Ten years ago, a three- or four-watt processor would suffice in an industrial or embedded PC," said David Fitzgerald, engineering manager at WinSystems. "Today we can put 30-to-50-watt processors on the same size board.  Designers must balance their system thermal requirements, power budget, and the required performance available from the computer.  Processors and chipsets have become much more efficient over the past few years, but they can use a lot of power and create a lot of heat."

So, almost every embedded-system designer aims to save power. To point designers in the right direction, we have assembled the following tips.


When possible, use on-chip I/O devices and turn-off unused peripherals. If you cannot turn off an I/O port or individual lines, tie unused pins high or low to eliminate floating inputs that can draw excessive power.

You may need to continuously power sensitive analog circuits to reduce the effects of thermal drift, long-term drift, and other error-inducing conditions. "For 14-and 16-bit ADCs in industrial products, those concerns are less of an issue today. You will still see minor drift with temperature changes, although significantly less than it was just a few years ago," noted Fitzgerald.

Engineers must understand the interactions among technologies and design techniques to get the most efficient use of power. Courtesy of Freescale Semiconductor. 
Engineers must understand the interactions among technologies and design techniques to get the most efficient use of power. Courtesy of Freescale Semiconductor.  
Take advantage of MCU capabilities that do not involve the CPU. A processor such as the Texas Instruments MSP430 lets a low-power ADC acquire data that a direct-memory-access (DMA) channel automatically places in memory without the need for any CPU cycles. After the DMA channel fills a memory array, it can signal the CPU to wake up and process the information. This type of action saves power and you will find this capability in other MCUs, too.

An Ethernet PHY must source enough power to drive a 100-meter cable, so it can consume from two to 10 times the power of a processor in a sleep mode. "Designers sometimes forget that when they put an MCU in a low-power mode, the Ethernet PHY continues to chirp away and consuming power," said John Weil, systems application manager at Freescale Semiconductor. "And if a system must answer broadcast messages, the MCU may wake up so often that designers do not get the power saving they expect."

Properly managed interrupts let an MCU remain in a low-power sleep state for long periods. Only when the MCU receives an interrupt request does it "awake" and take action programmed in an interrupt-service routine (ISR). Keep IRSs short and use internal MCU registers for counter values and temporary data storage. Transfers to and from on-chip RAM and flash memory, and continuous polling of I/O devices uses power and chews up CPU cycles.

When you use a register as a counter, count down rather than up. A down count automatically sets a flag when the count value reaches zero. But if you count up, you may need to obtain a value for a compare operation, which takes extra time and requires a memory transfer.

Power sources

Engineers must look at their power supplies, too. If you put an MCU into a low-power mode and your switch-mode power converter continues to operate, it may draw far more current than the processor chip. The combination of a switching converter and a low drop-out (LDO) regulator will help save power. "The MCU could use an output line to turn the switching converter off just before it enters a low-power mode," said Dave Freeman, system engineering manager, Power Management Business at Texas Instruments. "The MCU controls only the switcher, not the LDO. You set the switching converter to produce a voltage slightly higher than that from the LDO. Then, when the MCU comes out of sleep mode and turns on the switcher, the LDO will not have any current flow through it." A suitable LDO very low quiescent current.

This dual-regulator technique works best when you have a reasonable period, say, 10's to 100's of microseconds, between processor-power modes. "If your application wakes up the processor every micro-second, it changes the power load so often that you waste power as the switching converter responds to transient conditions," explained Freeman.

Power-conservation reaches to board-level products, too. "You can put a processor into a sleep mode that lets it return to full operation within microseconds or milliseconds," noted WinSystems' Fitzgerald. "In this light-sleep mode, you may see only a 10-percent power savings, but that is still significant when the board relies on power from batteries charged by solar cells in a remote location."

If you plan to wake up a processor from once a minute to once every few days, other low-power modes exist to put an SBC into a hibernation state. According to Fitzgerald, these modes can produce a 97-percent or higher reduction in power consumption.


Take advantage of on-chip memory. The C5000 DSP devices from Texas Instruments, for example, offer up to 256 Kbytes of on-chip memory--plenty for echo-cancellation and noise-reduction algorithms.

But, treat on-chip memory with care. Many processors supply flash memory that can keep up with a high-speed CPU, but flash-memory accesses can eat up a lot of power. So, engineers should balance their requirements for internal flash and RAM to obtain the best balance of performance and power efficiency. "Engineers often get a surprise when they see how much power flash memory draws," said Weil. "If they relocate code to the RAM, turn off the flash memory, and execute wakeup and sleep operations from RAM, their MCU will draw much less power."

Engineers also can reduce the power used by single-board computers (SBCs). Many processors let software control operating modes, from full power to hibernate. "The S3 mode--suspend to RAM--saves in RAM the register contents, the stack, and everything else the operating system (OS) needs to restart quickly, exactly where it left off before going into the suspend mode" said WinSystems' Fitzgerald. "Then, the powered-down CPU can quickly grab the information from RAM when it wakes up. To save more power, the OS can put the computer in the S4 mode--hibernate--that transfers key start-up information to a hard drive and then turns off the powers." For more information about processor sleep states as defined by the Advanced Configuration and Power Interface (ACPI), see: "For further reading."

Embedded systems that use double data-rate (DDR) memories can waste power because the terminating resistors on the memory buses always draw power. One of the new ColdFire processors from Freescale provides on-chip termination for DDR2 memory buses that do not waste power when the DDR2 memory is not active.

More savings

Designers also can make use of chip-based techniques such as dynamic voltage-and-frequency scaling (DVFS) and state-retention power gating (SRPG) that change operating voltages and operating frequencies on the fly or that remove power-hungry clocking/switching operations yet maintain flip-flop states with a low quiescent current. Processor vendors' data sheets and application notes explain these operations in detail.


Thanks go to John Dixon, low power DSP marketing manager and Kevin Belnap, product marketing manager, MSP430, both of Texas Instruments, for many tips and ideas they contributed for this column.

For further reading

For more information about Pentium and PCI Express power requirements and ACPI states, see: "PCI Express Architecture Power Management," at:

"Freescale Technologies for Energy Efficiency; 2007 Overview,"



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