Emerging Trends in Mil/Aerospace Embedded Systems: The new VPX backplane architecture, multi-core processors and the emergence of FPGA-based systems

Wed, 05/02/2007 - 5:22am
John Wemekamp, VP Strategic Planning/CTO, Curtiss-Wright Controls Embedded Computing

Several emerging new trends promise to shape the future direction of embedded system design for rugged, high performance defense and aerospace applications. In response to the ever increasing amount of high speed sensor data that systems are being tasked to process, in applications such as radar and signal processing, a new bus architecture, VPX (VITA 46) has been developed that goes far beyond the long popular VMEbus, providing the bandwidth required to support serial switch fabrics and increased levels of ruggedization including back and front metal covers (VPX-REDI) and electrostatic discharge (ESD) protection. This new architecture is backed by all the leading military COTS board vendors and many products, including SBCs, DSP engines and chassis have already been announced this year. Another important trend in MIL embedded design is the emergence of multi-core processors which reduce power dissipation while providing significant performance increases. Even better, multi-core processors are especially well suited to SMP (symmetric multiprocessing) which is increasingly popular in military applications. Processors from Freescale, Intel and P.A. Semi are bringing x86 and Power Architecture multi-core designs with long lifecycle support to the Mil market. The third important trend for embedded military systems is the increasing interest in reconfigurable computing. FPGAs, such as Xilinx's Virtex-5 are now fulfilling the promise of cost-effective reconfigurable computing for military applications, with low-power design and support for serial switch fabrics on the chip.

The VPX Era Begins

For over two decades, the VMEbus has maintained its position as the open standard bus architecture of choice for

Figure 1: Intel’s 1.67 GHz (@ 15W TDP) Core Duo processor powers Curtiss-Wright’s S/DCP3-1201 3U CompactPCI single board computer. The Core™ Duo’s ultra low voltage operation improves embedded system performance-per-Watt and is ideal for defense and aerospace platforms in which SWaP (Size, Weight, and Power) are critical.  
defense and aerospace applications. While this venerable VME parallel bus promises to continue its reign as the most popular embedded board standard for years to come, an emerging class of very demanding high-end applications such as real-time terrain mapping, radar and signal processing, requires a higher bandwidth bus architecture with even greater ruggedization features. In response, Curtiss-Wright, prime military integrators, and other COTS industry leaders, working together in the Vita Standards Organization ( have jointly developed the new VPX (VITA 46) standard and its complement, VPX-REDI (VITA 48). VPX combines VME’s successful 6U form-factor (a 3U variant is also defined) and 0.8” pitch chassis ecosystem with a new high bandwidth backplane connector, capable of supporting high-speed interconnects and serial switched fabrics such as Serial RapidIO (SRIO) and PCI Express (PCIe) to address the most demanding single board computer (SBC) and DSP engine applications. The VPX-REDI complement standard defines both 0.8” and 1.0” pitch variants. It also adds support for top and bottom metal covers, which together with the VPX standard’s new high-bandwidth connector’s built-in ESD protection, provides the level of rugggedization needed to support LRM (Line Replaceable Module) level maintenance of cards in the field, significantly reducing the cost and complexity of today’s more common replacement, and sparing, of complete subsystems (Line Replaceable Units or LRUs). Through the use of its new connector and optional protective covers, VPX is the first open standard board architecture to provide ESD protection of sensitive electronics, handling protection, and fault isolation.

Compared to VME, VPX also provides a significant increase in user definable I/O pins. The MultiGig RT2 provides the increased I/O pins and bandwidth required to handle high-speed signals and serial switch fabrics such as SRIO, which can require performance up to 3.125 Gb/s. This connector features tightly controlled impedance, low insertion loss, and less than 3% crosstalk at signaling rates up to 6.25 Gbaud. VPX also provides a significantly greater number of user I/O pins than are available from the VME64x or VXS (VITA 41) standards. A 6U VPX board provides a total of 192 high-speed differential pairs on its 432 signal contacts with 240 ground contacts on its 6 differential connectors. For 6U VPX mapped with VMEbus signals, the connector offers 32 pairs for a high speed fabric, 80 signals for VMEbus traffic, 128 pairs and 36 discrete signal contacts for user IO plus the required ground connections. In comparison, the legacy VME64x standard provides no differentially-routed connections to the backplane.

The multi-core Advantage

A second important trend in military embedded design is the recent emergence of multi-core processors which offer the dual benefits of reduced power dissipation and significant performance improvements. Processors from Freescale, Intel and P.A. Semi are bringing x86 and Power Architecture multi-core designs with long lifecycle support to the Mil market.

For the defense and aerospace embedded COTS market, where the most important equation is performance-per-Watt, the trend toward multi-core processors promises significant benefits since multi-core designs enable a doubling of performance without doubling power consumption. Combined with new power management techniques, the move to multi-core processors is enabling chip manufactures to produce lower power, higher performing processors. For SBCs integrating two or more processors onto one device saves real-estate for other important I/O features, such as integrated mass storage via a CompactFlash module or a high-performance serial backplane interface for cards built to the new VPX format.

Figure 2: The CHAMP-FX2, is a 6U VPX-REDI (VITA 46/48) compute engine that combines the flexibility of Xilinx FPGA-based reconfigurable computing, high performance Power Architecture (PowerPC) processing, and the high bandwidth of serial switched fabrics provided by the new VPX standards.  

Even better, multi-core processors are especially well suited to SMP (symmetric multiprocessing) which is increasingly popular in military applications. For example, multi-core processors are well suited for the intensive multitasking applications common to signal processing, mission computing and industrial control which typically have multiple processes and multiple tasks running in parallel within a process. These applications are often best addressed with a Symmetric Multi-Processing (SMP) operating systems. The list of SMP-capable operating systems such as Windows XP, Solaris, and Linux is growing with recent SMP versions of real-time operating systems including INTEGRITY from Green Hills Software and LynxSecure from LynuxWorks.

Another advantage of multi-core processor based SBCs is related to memory size. Instead of splitting memory between multiple CPUs a large global memory is available which is accessible by both (or all) of the processor cores. Data intensive applications, such as image processing and data acquisition systems, prefer larger memories able to access data at rates up to 100s of Mbytes/sec. These large memory applications benefit from the single large memory common in most multi-core designs.

A wide variety of VME and VPX SBCs that exploit the power of multi-core processors are already being offered, and many more will certainly be announced in the months ahead. Whatever the end-application, from medical imaging to military and aerospace, there is a multi-core CPU-based SBC that can provide the system developer with increased processing power and a richer I/O complement.

FPGAs Drive Reconfigurable Computing

The third significant trend emerging in the embedded military market, the growth of reconfigurable computing, is driven by an ever-increasing need for computational power amidst tight budgets and Space, Weight, and Power (SWaP) challenges. In the past, when faced with design challenges of maximizing performance and addressing SWaP requirements, the system integrator’s options would typically be to implement the system components in costly custom ASICs or to sacrifice system performance and/or features.

Today, FPGAs, less costly and complex than in previous years, are becoming a popular alternative to ASICs, providing integrators with an ideal alternative for satisfying feature/performance and environmental/cost requirements while meeting pressing time-to-market and time-to-deployment requirements.

Until recently, the use of FPGAs use has been typically limited to problems such as front-end I/O processing. Recent improvements in FPGA products, including significantly larger gate counts and software tools for development and integration, are now increasing their popularity. One of the significant improvement is the use of high-speed serial ports to connect FPGAs to a serial switching fabric, such as RapidIO. This trend provides a natural, high-speed, bidirectional data path that enables data movement at very high speeds. Examples of FPGAs that support high-speed serial ports include Xilinx’s Virtex-II Pro, Virtex-4, and Virtex-5. Matching the FPGA with the right processor has additional advantages beyond the data movement simplification mentioned earlier. For example, the Virtex-5 pairs especially well with Freescale’s dual-core 8641 processor because both connect to the same RapidIO fabric. Even better, the 8641 has two unique connections to the Virtex-5. The first is a select-map interface that enables multiple bitstreams to be stored in local Flash, SDRAM memory, or on a remote filesystem. Bitstreams can be rapidly loaded onto the user FPGAs at the command of the application running on the PowerPC, an important feature for systems with multimode requirements. The second unique connection provided by the 8641 is a local command bus. This bus gives the 8641 out-of-band access to the FPGAs for application-specific command and control, register setting, and so on, without disrupting the data flows into and out of the FPGA. An example of how serial ports can be implemented on a COTS FPGA board can be seen on Curtiss-Wright’s recently introduced the 6U VPX-based CHAMP-FX2, which connects each of its two Virtex-5 FPGAs to a four-lane port on its onboard Serial RapidIO (SRIO) switch.

These three trends in embedded defense and aerospace computing, the emergence of the VPX architecture, the greater availability of multi-core processors and improvements in FPGA components, work to strengthen the attractiveness of the COTS model for military applications. By ensuring that performance continues to grow and tracks state-of-the art speed and power requirements, COTS vendors enable their customers’ to out-source their hardware development needs, freeing them to focus their own efforts on their application, which is their greatest value-add.

John holds a B.S. in Electrical Engineering from Queens University in Kingston, Ontario. During his 22-year tenure at Dy 4, John filled a variety of increasingly responsible roles beginning as Hardware Design Engineer and various management roles through to his current role as Vice President, Strategic Planning and CTO. Prior to joining Dy 4, John successfully led a team at Bell Northern Research in the development of telecommunications product.


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