One key to great performance in a high-speed ADC is the linearity and noise of the input sample/hold circuit, involving a capacitor, amplifier and high-speed switches. To drive performance and speed, the capacitor needs to be somewhat large and the switches fast. In many low-power but high-speed ADCs, the input pins are directly connected to the sample/hold circuit, without buffering or isolation. Unfortunately, two primary issues exist with using non-buffered high-speed ADCs.
The first issue is the glitch energy of the sampling circuit. High speed and large capacitances lead to large glitches. Fortunately, the glitch energy is dealt with to an acceptable level in most cases by the use of a few extra passives at the ADC input pins. While this costs money and board space, it doesn't justify the inclusion of an integrated input buffer. The extra power consumption and even performance risk from the input buffer is not worth it for this benefit alone.
The second primary issue with a non-buffered ADC is the large sampling capacitor. Since noise due to capacitance is related by kT/C, a large capacitor is chosen to achieve low noise and high SNR. Driving a high capacitance at high frequency means driving low and decreasing impedance. Driving low impedances requires more drive current and pushes up the power consumption of the driving amplifier in order to get a full scale signal into the ADC. It means driving the amplifier to a higher output swing too, which often degrades its harmonic performance. The buffer’s exclusion from the ADC in order to save power in the ADC datasheet costs power and performance elsewhere. Therefore, the impedance issue primarily justifies integrating the input buffer.
Until recently, adding a buffer in a low-power CMOS high-speed ADC degraded SFDR/SNR performance to at best a 12-bit level and drove up power consumption to be non-competitive. An input buffer for a high-speed ADC was usually only found on BJT-based designs, where a linear buffer amplifier could be designed inside the ADC from a 5-V supply. However, in recent years a few low-power and high-performance ADCs have become available with an input buffer in low-voltage CMOS.
To study the impedance issue, the effective parallel input resistance and capacitance of a buffered (ADS61B49) and non-buffered (ADS6149) ADC are chosen from their respective datasheet equivalent input circuits. These circuits are analyzed and converted into an equivalent parallel R and C across the differential input pins; like a Smith chart broken into R and C for a system that remains on the capacitive side of the Smith chart. The equivalent parallel R and C loads were used to model the ADCs in Figures 1a and 1b.
An ADC of this type is typically used with a transformer to convert a single-ended drive source to a differential input at the ADC input pins. It is common to match the ADC to a target impedance; 50 Ohms was used for this analysis. The system circuit that is analyzed here is shown in Figures 1a and 1b. The 1:1 turn’s ratio transformer transfers impedance at a 1:1 ratio to the input side of the transformer. In Figure 1, note that 25 Ohms + 25 Ohms is placed on the ADC side of the transformer to form a 50-Ohm differential load seen by the source. However, in addition to the expected load, many other passives are present in Figure 1a. The differential filter seen at the ADC input pins is there to attenuate the high-frequency glitch associated with the sampling circuit that otherwise would ‘kick-back’ from the non-buffered ADC, disturb its inputs, and detrimentally get converted as part of the signal.
A high-impedance buffered input provides improved insertion loss because the voltage standing wave ratio (VSWR) is maintained closer to the ideal of 1.0 as input frequency increases. VSWR is a measure of how much of the signal is transferred to the load (the ADC) versus reflected back to the source due to impedance mismatch. At low frequency, the benefit is not as substantial, but becomes more so at higher frequency. The buffered ADC input impedance is so much higher than the target of 50 Ohms that it barely interacts as a parallel circuit. The bigger the difference between the ADC impedance and the intended load seen by the source, the more control one has to set that impedance on the board.
Using the Figure 1 circuits, the VSWR is analyzed up to an input frequency of 500 MHz. The degrading VSWR results in a degradation in signal transfer, shown in Figure 2.
There are different ways to take advantage of the buffered input besides achieving less insertion loss at 50 Ohms with a 1:1 transformer. If a 1:2 turns ratio transformer is used, it will provide 6 dB voltage gain as a passive circuit. However, it has a 1:4 impedance transfer and requires a 200-Ohm target at the ADC input side of the transformer, if the source is 50 Ohms. Achieving 200 Ohms without the buffer is difficult but possible at a spot frequency by inflating the board load above 200 Ohms to achieve a net 200 Ohms at that frequency, after the board load resistors and ADC input resistance is calculated in parallel. For wideband systems this means higher impedance (than the target) below the spot frequency, and much lower above it. This translates into a large droop in signal transfer across a wideband frequency for a non-buffered ADC. Therefore, it is more practical to consider the 1:2 transformer with a high-impedance buffered input, or for narrow-band high IF signal conversion without the buffer.
Some communications signals such as cellular LTE and WiMAX have 20+MHz bandwidth signals on the horizon. Linearizing the power amplifier for these applications requires observing 100+MHz bandwidth signals from the power amplifier in order to correct the harmonics using pre-distortion algorithms. This requires 250+MSPS ADCs capable of capturing this bandwidth simultaneously with good performance, commonly above the first Nyquist zone (>125 MHz for 250 MSPS) where the input impedance is falling rapidly and the integrated input buffer can be of greatest assistance.
Philip M. Pratt is the Product Marketing Engineer for High-Speed Data Converters at Texas Instruments. Philip received his BSEE from the University of Tennessee, Knoxville, and MSEE from Florida Institute of Technology, Melbourne.