A major challenge facing power engineers today is how to overcome a reduction in board space for the power circuitry in commercial electronic products. A quick walk through any electronics retail store will reveal that personal computers have become smaller and even miniaturized which is a trend for many other types of electronic devices. Just as the size of these products is being reduced, their functionality is increasing. The trend of more utility in less space means that the area left for the power circuitry is diminished which creates a tough set of challenges when managing the thermals, power loss, and layout.
One way engineers have met this challenge is by utilizing advancements in MOSFET silicon technology and packaging which have resulted in higher-performance devices in smaller-size packages. With this trend, we have seen a migration from standard leaded packages like SO-8s to power packages with bottom side drain pads. For high-current applications, this has usually been a power 6-mm x 5-mm package such as the PowerPAK® SO-8. However for lower current applications, the trend is migrating towards the power 3-mm x 3-mm package such as the PowerPAK 1212-8. Because RDS(on) levels are now low enough in this package, it has become popular for 10-A dc-to-dc applications in notebook PCs.
Even though the power 3-mm x 3-mm package helps shrink dramatically the space used for the dc-dc circui, there are still opportunities to reduce space requirements even more and also increase power density. One way to accomplish this is to replace discrete single-channel MOSFETs with packages combining two devices. Dual SO-8 power MOSFETs have been around a long time, but typically they can only handle load currents of less than 5 A, which is fine for the 5-V and 3.3-V rails in notebooks and netbooks but obviously too low for systems with loads of 10 A and higher.
This is why manufacturers are working to make dual power packages for MOSFETs that allow a much higher potential maximum current capability and better thermals than traditional surface mount packages. By employing the basics of the power package style and combining two separate chips in one package, such devices reduce the real estate needed for the power circuitry.
One such package type called PowerPAIR combines outline dimensions that are smaller than a single power 6x5 package (PowerPAK SO-8) with a maximum current rating of 15 A. Traditionally in notebook computers this type of load current would be designed with two power 6x5 packages, taking up more than 60 mm² in area after taking into account the area for traces and labeling and the positioning of the two devices. The dimensions of this power dual package are 6.0 mm by 3.7 mm resulting in an area of 22 mm² consumed in board space. A 63 % reduction in board space is helpful then to the power engineer who is given less and less space for the power circuitry. This type of advantage was not available before with the traditional SO-8 dual package types.
In addition to saving space compared to two power 6x5 packages or two SO-8 packages, this device can simplify designs and save some space for engineers who are presently using two power 3x3 packages. As mentioned earlier, the power 3x3 package has become a trend in many computing applications in the 10-A range since the package is smaller and runs cooler than the standard SO-8 package typically used. The power dual package can easily replace two power 3x3 packages with one part and even provide some space savings given again to layout and marking on the PCB as shown in Figure 1. Therefore, it is a logical design step for dc-dc applications from 5A to 15A and a way to increase power density.
The dual PowerPAIR power package uses an asymmetric structure which lends itself to dc-dc buck converter designs. Its design accommodates and optimizes the die for the high side MOSFET and low side MOSFET for the buck converters. This means, as shown in Figure 2, the low side MOSFET has a lower on resistance than the high side which accounts for the difference in the size of the pad regions.
In fact the on-resistance of the low side MOSFET is the key feature of the device. Even with the reduced package size, it is still possible to attain an RDS(on) rating of less than 5 milliohms maximum at 4.5 V. This helps boost efficiency at the max loads and keeps the device running cooler despite its compact size.
Another advantage of this device is its layout. As can be seen from Figure 2, the pinning of the package makes it simple to integrate into a buck converter design. More specifically, the input is on one side of the device and the output on the other. Pins 2 and 3 are matched to the VIN of the dc-to-dc circuit, which is the drain of the high-side MOSFET. The small pad is also the drain pad for the high-side component. The larger pad is the switch node of the circuit where the source of the high-side MOSFET and the drain of the low-side MOSFET are connected internally to the device. This is the node which is connected to the inductor. Lastly the ground connects are pins 4 and 5 which is the source of the low-side MOSFET. Pins 1 and 6 are the gates connections for the high side and low side MOSFET respectively. This layout makes it simple and reduces the chances for layout errors when trying to use two devices. It may also reduce the parasitic inductances associated with extra PCB traces needed for combining multiple devices.
The last benefit of moving to power dual packages in this reduced form factor is the level of efficiency that can be achieved which effectively helps increase power density. The device was mounted on a single phase buck converter evaluation board with the following conditions:
VIN = 12 V, VOUT = 1.05 V, VDRIVE = 5.0V, fsw = 300 kHz, and IOUT max. = 15 A
Efficiency was measured across the load range. At 15 A, efficiency was 87 % and the case temperature of the device was measured at just under 70°C. Peak efficiency was above 91.5 %. This type of performance helps reduce power loss and save energy in electrical systems while still allowing for a compact design.
The power dual package in the 6.0mm x 3.7mm form factor is an exciting development in MOSFET packaging technology. It gives the engineers the option to improve, shrink, and simplify designs while maintaining high levels or performance demanded in today’s consumer electronics.