The flood of analog-to-digital converters (ADCs) makes it difficult to know which ADC best fits a given application. All too often when engineers select ADCs, they simply look at bits, signal-to-noise ratio and harmonic performance. But other specifications have equal importance, often in unanticipated ways. I will review nine of the most-overlooked specs and explain how they influence ADC performance. (See: For further reading.)

1. SNR Trumps Resolution

Perhaps the most misunderstood specification for an ADC is the number of bit of resolution it provides. This spec fails to explain any performance capabilities of the ADC itself. But you can use the number of bits, n, to calculate the theoretical signal-to-noise ratio (SNR) for an ADC: SNR = 6.02 × n + 1.76.

But engineers may not know that thermal noise, clock jitter, differential non-linearity (DNL) errors and other anomalies limit an ADC's SNR. This is especially true for high performance, high resolution converters. Some datasheets provide an Effective Number of Bits (ENOB) spec that describes the number of meaningful bits an ADC will provide. To calculate an ADC's ENOB value, put the measured SNR value into the equation above and solve for n. ENOB provides a useful spec, but noise spectral density specified in either dBm/Hz or  nV   offer a more useful gauge of ADC performance.  

This chart shows how power supply rejection ratio (PSRR) increases with frequency. Proper filtering can reduce noise and its effects on measurements.

Many engineers are also concerned with an ADC's spurious distortion and rejection of harmonics. They may not understand that harmonic performance and spurious distortion are completely separated from the ADC's resolution spec. In fact, the resolution of the ADC has no relation to the distortion behavior of the converter. Designers of ADCs adjust their IC-design characteristics so harmonics fall into line with expectations for an ADC with n-bit resolution. So, when you select a converter, pay close attention to its SNR and spurious-free dynamic range (SFDR), but keep these specs separate from the ADC's specified bits of resolution.

2. Look at Power-Supply Noise

A power-supply rejection ratio (PSSR) describes of the amount of noise signal on the power-supply lines that couples to the ADC's sample network. That noise then appears as part of the ADC's digital-output value. Many ADCs have a PSRR of only 30 dB to 50 dB. Thus, noise and signals present on the power supply lines will appear in the ADC's output only 30 dB to 50 dB below the converter's input signal. A PSRR value increases with the frequency of power-supply noise (Figure 1).

Typically, you use the power supply "noise" and the converter's input range to calculate PSSR. So, for power-supply noise of 20 mV rms at the ADC power pins and full-scale converter range of 0.7V rms, you obtain a PSSR value of -31 dB full-scale (dBFS). If the converter has a 30 dB PSRR rating, then the noise (assuming a coherent signal) would show up as a -61 dBFS spectral line in the ADC's output.

The PSRR information helps determine how much filtering and decoupling you must provide at the ADC's power supply pins. The PSRR becomes acutely important in any circuit that may experience excess noise on power-supply outputs. Noise can arise from a switching supply, a circuit — such as a transmitter — that places large common-mode signals on power supply outputs and grounds, and circuits that operate in magnetic or electrostatic environments. Failure to either design a power-supply network that meets the requirements of the ADC in terms of PSRR or failure to select an ADC with suitable PSRR for the selected supply will result in increased converter noise and degraded spectral performance.

Figure 2. A plot of values from a single-ended ADC (a) shows how noise on a signal affects results. The values plotted in (b) come from a differential-input ADC that effectively reduces common-mode noise.

3. Reject Common-Mode Signals

An ADC's common-mode rejection ratio (CMRR) specifies how well it will reject a common-mode signal in the presence of the differential signal you want the ADC to measure. Many ADCs employ differential inputs that greatly reduce the effects of common-mode signals present in a system. And differential inputs inherently reject even order distortion products. Common-mode noise can come from power-supply ripple, high-power signals induced on ground planes, RF leakage through mixers and filters and high-intensity electric and magnetic fields. Many times, CMRR is not specified, so engineers who require a converter's CMRR data they must either asking the ADC vendor for the data or use the ADC vendor's eval boards to perform characterization tests.

Many converters have a CMRR of between 50 dB and 80 dB. Figure 2 plots digital values for an ADC in a single-ended circuit (a) in which the common-mode noise signal became part of the analog input and was digitized accordingly. The plot in (b) shows how the same ADC configured with differential inputs almost completely rejected the noise.

Clock Specs Count, Too

The quality of the clock signals applied to an ADC can affect performance more than expected. Unfortunately, not all ADC vendors provide clock data and at times you may find it difficult to determine clock specifications.

4. Keep Slew Rate High

An ADC's clock-input slew rate specifies the minimum slew rate needed to achieve the converter's rated performance. Most contemporary converters have an input-clock buffer with sufficient gain to properly define a sample instant — the time at which the ADC samples the input signal. A slow slew rate, however, can cause uncertainty in the sample-instant timing, and excess noise on the digital output will result. To achieve an ADC's rated noise performance, engineers should meet or exceed the minimum clock-input slew-rate spec. (See references 1 and 2.)

5. Jitter Increases Measurement Error

 Aperture jitter relates an ADC's internal clock uncertainty, also called jitter, to the ADC's SNR, as shown in the equation below:

SNR=20log(2 × π × f_analog × t_jitter)

Figure 3. A small amount of jitter on an ADC's clock signal can cause a significant measurement error, shown here for the upward portion of a sampled sine wave.

As shown in Figure 3, a small amount of clock jitter will vary the sampling point on the ADC input signal and thus can create a large measurement error. In low-frequency applications, jitter may have an inconsequential effect, but as the frequency of the measured signal increases, noise due to jitter also increases. An ADC datasheet specifies aperture jitter only for the converter. You must also take into account external clock-signal jitter, which adds to internal aperture jitter in an rms manner (the square root of sum of squares). Failure to use a clock signal with adequately low jitter will result in poorer-than-expected ADC performance.

In addition to increased noise from clock jitter, an additional noise phenomenon occurs during the sample process. The ADC sample process comprises, in part, convolution in the frequency domain. As such, any non-harmonic components of the clock signal will be convolved onto the digitized output, and it will appear as output distortion. Therefore, the clock signal you supply to an ADC should have the highest spectral purity possible and posses a maximum jitter as defined by your application and the equation above.

6. Account for Aperture Delay

An aperture delay occurs between when you apply a CONVERT strobe to an ADC and when it actually samples the unknown analog signal. Contemporary converters have short aperture delays; on the order of a nanosecond or less. The delay may be positive, negative or even zero. A negative aperture delay indicates that the analog signal path includes a longer delay than the convert strobe path. This results in a sample instant that appears to occur before the convert signal is applied. For many applications, aperture delay is unimportant. However, if you must know an exact sample instant, then aperture delay becomes important. (Most datasheets specify a typical aperture delay, not worst case.)

7. Conversion Time and Latency

Conversion time and latency are closely related specifications. Analog-to-digital conversions do not occur instantly. In a successive-approximation converter, for example, it generally takes at least n clock cycles for an n-bit conversion. So, a delay — the conversion time — occurs between applying a CONVERT strobe to the ADC and the output of the digital value. (An output pin signals the ADC's conversion-complete status.)

ADCs that employ a pipelined topology have an inherent conversion latency that directly corresponds to the number of pipelines or internal digital stages used to produce a digital output. Conversion latency is usually stated in terms of pipeline delays. You can calculate the actual conversion time by multiplying this latency by the period of the sample clock used in the application.  Both of these specifications play important roles when you must accurately account for time, as in a feedback loop.

8. Wake Up an ADC

To save power, some circuits may power down an ADC during inactive periods. This technique conserves power, but after power up, an ADC requires time for its internal references and clock to stabilize. During this start-up period, conversions can produce anomalous results. To ensure accurate conversions, a system must wait until the ADC vendor's specified start-up time before it uses any conversion results. Turn on an ADC sufficiently early to guarantee accurate data at the time you need it.

9. Do Not Overload Outputs

ADC datasheets specify a drive capability for digital outputs. But, if you use the maximum drive current, you can compromise converter performance. In a practical circuit, a 10 pF capacitive load driven by an ADC's CMOS output that slews at 1 V/nsec will draw 10 mA during the slew. If 16 bits switch simultaneously, total current could reach 160 mA. An internal resistance of only 0.1Ω would cause a 16 mV voltage drop. In a 16-bit converter with a 2V input range, potential noise would "swamp" the ADC's nine LSBs.

To reduce a voltage drop on the ADC's supply pins, you must minimize output loading, properly decoupled power-supply inputs and optimize PCB layouts. Many converters now provide low-voltage differential signaling (LVDS) outputs. These outputs reduce switching currents and thus improve performance.

PCB Layout Affects Performance

Although PCB design requirements usually don't appear in datasheets, the signal and power layout can greatly affect converter performance. A poor layout always results in degraded performance. If a circuit fails to include sufficient decoupling capacitors, for example, circuits will "see" excess power supply noise. Because an ADC has a finite PSRR characteristic, this noise will couple into the analog inputs and corrupt the digital output "spectrum" of the ADC data as shown in Figure 4. Other specifications such as CMRR and input impedance have similar sensitivities. And, engineers might forget that noise may modulate the ADC's clock signal which convolves the noise with the analog input and results in additional spurious signals.

Figure 4. Adequate decoupling capacitors enhance ADC performance (a). The lack of enough capacitance on power supply inputs degrades performance as seen in (b).

When engineers select a converter for an application, they should consider all of the device's specifications — even those that may seem unimportant. It is those "unimportant" specs that often limit ADC performance in a design.

For further reading

For more details about ADC specifications, see "Understanding High Speed ADC Testing and Evaluation," AN-835, Analog Devices. www.analog.com.

References

¹ "Aperture Uncertainty and ADC System Performance", AN-501, Analog Devices.

² "Sampled Systems and the Effect of Clock Phase Noise and Jitter", AN-756, Analog Devices.

Brad Brannon is a Systems Applications Engineer for the High Speed Converters Group at Analog Devices. He has been with ADI since 1984, and he specializes in analog-to-digital converters and wireless systems. Brad graduated for North Carolina State University with a BS in electrical engineering. Contact Analog Devices Inc., 3 Technology Way, Norwood, MA 02062; (781) 329-4700; www.analog.com.